EPM7064SLC44-7 Altera, EPM7064SLC44-7 Datasheet - Page 8

• Manufacturer Part Number: EPM7064SLC44-7
• Description: IC MAX 7000 CPLD 64 44-PLCC
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7064SLC44-7

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 36
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Family Name: MAX 7000S
• # Macrocells: 64
• Number Of Usable Gates: 1250
• Frequency (max): 166.7MHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 36
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1196-5

MAX 7000 Programmable Logic Device Family Data Sheet
Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
8
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
6 to 16 I/O Pins
6 to 16 I/O Pins
INPUT/OE1
Control
Control
Block
Block
I/O
I/O
6
6
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Figure 2
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macrocell arrays, as shown in
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
LAB A
LAB C
Macrocells
Macrocells
shows the architecture of MAX 7000E and MAX 7000S devices.
33 to 48
1 to 16
6 to16
6 to16
16
16
36
36
PIA
36
36
6 to16
6 to16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Control
Control
Block
Block
I/O
I/O
Altera Corporation
6
6
Figures 1
6 to 16 I/O Pins
6 to 16 I/O Pins
and 2.