IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLC44-6

Manufacturer Part NumberEPM7064SLC44-6
DescriptionIC MAX 7000 CPLD 64 44-PLCC
ManufacturerAltera
SeriesMAX® 7000
EPM7064SLC44-6 datasheet
 


Specifications of EPM7064SLC44-6

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max6.0ns
Voltage Supply - Internal4.75 V ~ 5.25 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o36Operating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case44-PLCC
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Features-  
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September 2005, ver. 6.7
Features...
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the
Data Sheet
Sheet.
Table 1. MAX 7000 Device Features
Feature
EPM7032
EPM7064
Usable
600
1,250
gates
Macrocells
32
Logic array
2
blocks
Maximum
36
user I/O pins
t
(ns)
6
PD
t
(ns)
5
SU
t
(ns)
2.5
FSU
t
(ns)
4
CO1
f
(MHz)
151.5
151.5
CNT
Altera Corporation
DS-MAX7000-6.7
®
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
Tables 1
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
MAX 7000A Programmable Logic Device Family
or the
MAX 7000B Programmable Logic Device Family Data
EPM7096
EPM7128E
1,800
2,500
64
96
128
4
6
8
68
76
100
6
7.5
7.5
5
6
6
2.5
3
3
4
4.5
4.5
125.0
125.0
MAX 7000
Programmable Logic
Device Family
Data Sheet
®
architecture
and 2)
EPM7160E
EPM7192E
EPM7256E
3,200
3,750
5,000
160
192
256
10
12
104
124
164
10
12
7
7
3
3
5
6
100.0
90.9
90.9
16
12
7
3
6
1

EPM7064SLC44-6 Summary of contents

  • Page 1

    ... CO1 f (MHz) 151.5 151.5 CNT Altera Corporation DS-MAX7000-6.7 ® High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 Includes 5 ...

  • Page 2

    ... Fast input setup times provided by a dedicated path from I/O pin to macrocell registers – Programmable output slew-rate control Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations EPM7160S EPM7192S 3,200 ...

  • Page 3

    ... General The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with Description advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds 175.4 MHz. MAX 7000S devices in the -5, -6, ...

  • Page 4

    ... Power-saving mode Security bit PCI-compliant devices available Notes: (1) (2) 4 Table 4. Feature (2) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. The MultiVolt I/O interface is not available in 44-pin packages. EPM7032 All EPM7064 MAX 7000E EPM7096 Devices Altera Corporation All MAX 7000S Devices ...

  • Page 5

    ... Perform a complete thermal analysis before committing a design to this device package. For more information, see the Operating Requirements for Altera Devices Data MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The ...

  • Page 6

    ... MAX 7000 devices to be used in mixed-voltage systems. The MAX 7000 family is supported byAltera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)— ...

  • Page 7

    ... Control I/O pins Block Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin ...

  • Page 8

    ... MAX 7000E and MAX 7000S devices. LAB Macrocells to16 6 to16 PIA LAB Macrocells to16 6 to16 6 Output Enables LAB B 6 to16 6 to16 Macrocells I I/O Pins Control Block 6 LAB D 6 to16 6 to16 Macrocells I I/O Pins Control Block 6 Figures 1 Altera Corporation and 2. ...

  • Page 9

    ... Logic Array 36 Signals 16 Expander from PIA Product Ter Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: ■ 36 signals from the PIA that are used for general logic inputs ■ Global controls that are used for secondary register functions ■ ...

  • Page 10

    ... operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. 10 shows a MAX 7000E and MAX 7000S device macrocell ...

  • Page 11

    ... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: ■ global clock signal. This mode achieves the fastest clock-to- output performance. ■ global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock ...

  • Page 12

    ... OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. 12 Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders ) is incurred when SEXP Figure 5 shows how shareable expanders Product-Term Select Matrix Altera Corporation Macrocell Product-Term Logic Macrocell Product-Term Logic ...

  • Page 13

    ... Figure 6. Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. 36 Signals 16 Shared from PIA Expanders Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet ). For example macrocell requires 14 product terms, the PEXP . PEXP Figure 6 ...

  • Page 14

    ... The I/O control block of MAX 7000E and MAX 7000S devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. 14 PIA Signals Figure 7 shows how To LAB . Figure 8 shows the I/O CC Altera Corporation ...

  • Page 15

    ... Figure 8. I/O Control Block of MAX 7000 Devices EPM7032, EPM7064 & EPM7096 Devices MAX 7000E & MAX 7000S Devices Note: (1) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet VCC OE1 OE2 GND From Macrocell To PIA PIA To Other I/O Pins From ...

  • Page 16

    ... Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. ...

  • Page 17

    ... EEPROM cells. This process is repeated for each EEPROM address. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address ...

  • Page 18

    ... Sum of the fixed times to erase, program, and PPULSE verify the EEPROM cells Cycle = Number of TCK cycles to program a device PTCK f = TCK frequency TCK Cycle VTCK = t + -------------------------------- VPULSE f TCK = Verify time VER t = Sum of the fixed times to verify the EEPROM cells VPULSE Cycle = Number of TCK cycles to verify a device VTCK Altera Corporation ...

  • Page 19

    ... EPM7064S 0.06 0.09 EPM7128S 0.08 0.14 EPM7160S 0.09 0.16 EPM7192S 0.11 0.18 EPM7256S 0.13 0.24 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Values TCK Programming t (s) Cycle PPULSE PTCK 4.02 342,000 4.50 504,000 5.11 832,000 5.35 1,001,000 5 ...

  • Page 20

    ... ACL CPPW level, input voltage thresholds are at TTL levels, and CCINT is connected to a 3.3-V supply, the output high is CCIO levels lower than 4.75 V incur a nominally greater CCIO instead of t OD2 TM option turned on) ) for the t LPA LAD parameters. . OD1 Altera Corporation , LAC IC ...

  • Page 21

    ... MAX 7000 devices can be programmed on Windows-based PCs with the Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the device ...

  • Page 22

    ... MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. 1149.1-1990. 1149.1 (JTAG) MAX 7000 family. The pin-out tables (see the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out Boundary-Scan information) show the location of the JTAG control pins for each device. ...

  • Page 23

    ... Table 11. 32-Bit MAX 7000 Device IDCODE EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Notes: (1) (2) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet 11 show the boundary-scan register length and device IDCODE Table 10. MAX 7000S Boundary-Scan Register Length Device EPM7032S EPM7064S EPM7128S EPM7160S ...

  • Page 24

    ... MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 Figure 9. MAX 7000 JTAG Waveforms Captured Table 12 devices. Symbol f For more information, see Boundary-Scan Testing in Altera 24 shows the timing requirements for the JTAG signals. TMS TDI t JCP t t JCH JCL TCK t JPZX ...

  • Page 25

    ... QFP leads. The Development carrier is used with a prototype development socket and special programming hardware available from Altera. This carrier technology Socket makes it possible to program, test, erase, and reprogram a device without exposing the leads to mechanical stress. ...

  • Page 26

    ... C –65 135 ° C 150 ° C 135 ° C Min Max Unit 4.75 5.25 V (4.50) (5.50) 4.75 5.25 V (4.50) (5.50) 3.00 3.60 V (3.00) (3.60) 4.75 5.25 V –0.5 ( 0.5 V CCINT CCIO 0 70 ° C –40 85 ° ° C –40 105 ° Altera Corporation ...

  • Page 27

    ... I/O Table 18. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Symbol Parameter C Dedicated input pin capacitance IN C I/O pin capacitance I/O Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (9) Conditions = – 4.75 V (10) OH CCIO = – 3.00 V ...

  • Page 28

    ... V Output Voltage (V) O Timing Model MAX 7000 device timing can be analyzed with the Altera software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in devices have fixed internal delays that enable the designer to determine the worst-case timing of any design. The Altera software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation ...

  • Page 29

    ... External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. relationship of internal and external delay parameters. f For more infomration, see Timing). Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Internal Output Enable Delay t (1) IOE ...

  • Page 30

    ... GLOB Global Clock at Register Array Clock Mode ACH Clock into PIA t PIA Clock into Logic Array Clock at Register Data from Logic Array t to Logic Array to Pin t PIA t SEXP LAC LAD t PEXP t COMB ACL PIA CLR t OD Altera Corporation PIA PRE t OD ...

  • Page 31

    ... Minimum array clock period ACNT f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 19 through 26 show the MAX 7000 and MAX 7000E AC operating conditions. Conditions -6 Speed Grade Min ...

  • Page 32

    ... Altera Corporation Unit ...

  • Page 33

    ... Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency Maximum clock frequency f MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions MAX 7000E (-10P) MAX 7000 (-10) Min 7.0 0.0 (2) 3.0 (2) ...

  • Page 34

    ... Altera Corporation ...

  • Page 35

    ... Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency Maximum clock frequency f MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions MAX 7000E (-12P) Min 7.0 0.0 (2) 3.0 (2) 0 ...

  • Page 36

    ... Altera Corporation ...

  • Page 37

    ... Minimum global clock period CNT f Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -15 Min Max 15 15.0 11.0 0.0 (2) 3.0 (2) 0 ...

  • Page 38

    ... Altera Corporation Unit ...

  • Page 39

    ... Output data hold time after ODH clock t Minimum global clock period CNT f Maximum internal global clock CNT frequency t Minimum array clock period ACNT Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet = 3.3 V ± 10% for commercial and industrial use LAD LAC IC EN SEXP Tables 27 ...

  • Page 40

    ... Altera Corporation Unit MHz MHz Unit 0.5 ns 0.5 ns 1.0 ns 5.0 ns 0.8 ns 5.0 ns 5.0 ns 2.0 ns 1 ...

  • Page 41

    ... Global clock high time CH t Global clock low time CL t Array clock setup time ASU t Array clock hold time AH Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions -5 Min Max (7) 1.1 (8) 12.0 = 3.3 V ± 10% for commercial and industrial use. ...

  • Page 42

    ... Altera Corporation Unit MHz ns MHz MHz Unit 0.5 ns 0.5 ns 1.0 ns 5.0 ns 0.8 ns 5 ...

  • Page 43

    ... PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0 the PIA timing value. (8) The t parameter must be added to the t LPA running in the low-power mode. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -5 Min Max Min Max Min Max Min Max 1.9 0.6 1 ...

  • Page 44

    ... Altera Corporation Unit MHz ns MHz MHz ...

  • Page 45

    ... Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions -6 Min Max Min Max Min Max Min Max 0.2 0.2 2.6 3.7 1.1 3.0 3.0 ...

  • Page 46

    ... Altera Corporation for more parameter Unit 15 13.0 ns MHz ...

  • Page 47

    ... Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -6 Min Max Min Max Min Max Min Max 6.7 (4) 149.3 122.0 (5) 166.7 166.7 Conditions ...

  • Page 48

    ... Speed Grade -10 -15 Max Min Max Min 7.5 10.0 7.5 10.0 7.0 11.0 0.0 0.0 3.0 3.0 0.5 0.0 4.7 5.0 4.0 5.0 4.0 5.0 2.0 4.0 Altera Corporation Unit 4.0 ns 2.0 ns 13.0 ns for more parameter LPA Unit Max 15 ...

  • Page 49

    ... Output buffer enable delay ZX1 t Output buffer enable delay ZX2 t Output buffer enable delay ZX3 t Output buffer disable delay XZ t Register setup time SU Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -7 Min Max 1 7.8 3.0 3.0 (2) 3 (3) 1.0 8 ...

  • Page 50

    ... Table 14. See Figure 13 parameter into the signal LAD , t , and t parameters for macrocells ACL CPPW Altera Corporation Unit Max 1.0 ns 1.0 ns 6.0 ns 6.0 ns 1.0 ns 4.0 ns 4.0 ns 2.0 ns 13.0 ns ...

  • Page 51

    ... Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet and 38 show the EPM7256S AC operating conditions. Note (1) Conditions -7 Min Max 7 ...

  • Page 52

    ... Altera Corporation Unit ...

  • Page 53

    ... Supply power (P) versus frequency (f is calculated with the following equation: Consumption The P and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera The I application logic, is calculated with the following equation: I CCINT A × MC The parameters in this equation are shown below: ...

  • Page 54

    ... EPM7192S 0.93 EPM7256S 0.93 estimate based on typical conditions 0.52 0.144 0.74 0.144 0.74 0.144 0.54 0.096 0.54 0.096 0.54 0.096 0.54 0.096 0.40 0.040 0.40 0.040 0.40 0.040 0.40 0.040 0.40 0.040 0.40 0.040 values should be verified during Altera Corporation ...

  • Page 55

    ... Typical Active (mA) 55.5 MHz 1 50 Low Power Frequency (MHz) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 14 shows typical supply current versus frequency for MAX 7000 devices. EPM7064 151.5 MHz High Speed Typical I Active (mA) 100 150 200 ...

  • Page 56

    ... Room Temperature 400 100 MHz 300 High Speed 200 47.6 MHz 100 Low Power 0 50 100 150 Frequency (MHz) 750 Room Temperature 600 90.9 MHz 450 High Speed 300 43.4 MHz 150 Low Power 100 Frequency (MHz) Altera Corporation 200 125 ...

  • Page 57

    ... CC 160 Active (mA 56.2 MHz 80 Low Power 100 Frequency (MHz) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet shows typical supply current versus frequency for MAX 7000S EPM7064S 142.9 MHz Typical I CC High Speed Active (mA) 150 200 EPM7160S 147.1 MHz ...

  • Page 58

    ... V CC Room Temperature Typical I CC Active (mA) 180 120 Low Power Frequency (MHz) Device See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Pin-Outs 58 EPM7256S 125.0 MHz High Speed Typical I CC Active (mA) 55.6 MHz 75 100 125 Room Temperature ...

  • Page 59

    ... The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. (2) JTAG ports are available in MAX 7000S devices only. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet through 22 show the package pin-out diagrams for MAX 7000 ...

  • Page 60

    ... The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. 60 I/O 59 I/O 58 GND I/O/(TDO) ( I/O 55 I/O 54 I/O 53 VCCIO 52 I/O 51 I/O EPM7064 50 I/O/(TCK) (2) 49 I/O EPM7096 48 GND 47 I/O 46 I/O 45 I/O 44 I/O Altera Corporation ...

  • Page 61

    ... Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM7160S devices. (2) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. (3) JTAG ports are available in MAX 7000S devices only. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet I/O 12 VCCIO ...

  • Page 62

    ... Figure 20. 160-Pin Package Pin-Out Diagram Package outline not drawn to scale EPM7192E J H Bottom View 160-Pin PGA 62 Pin 81 Pin 1 Pin 51 Pin 26 Pin 1 Pin 41 Pin 76 EPM7064S EPM7128S EPM7160S Pin 51 100-Pin TQFP EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E 160-Pin PQFP Altera Corporation Pin 121 Pin 81 ...

  • Page 63

    ... Figure 21. 192-Pin Package Pin-Out Diagram Package outline not drawn to scale. Figure 22. 208-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 53 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet EPM7256E K Bottom J View 192-Pin PGA EPM7256E EPM7256S 208-Pin PQFP/RQFP ...

  • Page 64

    ... ISP & ICR via an Embedded Processor. Added Tables 6 through 8. Added “Programming Sequence” section on page 17 “Programming Times” section on page 18. Updated text on page 16. Added Note (5) on page 28. Updated the “Open-Drain Output Option (MAX 7000S Devices Only)” section on page 20. and Altera Corporation ...

  • Page 65

    ... Notes: Altera Corporation 65 ...

  • Page 66

    ... Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...