EPM7064STI44-7 Altera, EPM7064STI44-7 Datasheet - Page 53

IC MAX 7000 CPLD 64 44-TQFP

EPM7064STI44-7

Manufacturer Part Number
EPM7064STI44-7
Description
IC MAX 7000 CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064STI44-7

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000S
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
166.7MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
36
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2023
EPM7064STI44-7

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Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Power
Consumption
Altera Corporation
These values are specified under the recommended operating conditions shown in
information on switching waveforms.
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
The f
Operating conditions: V
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
The t
running in the low-power mode.
LPA
MAX
parameter must be added to the t
values represent the highest frequency for pipelined data.
CCIO
Supply power (P) versus frequency (f
is calculated with the following equation:
P = P
The P
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera
The I
application logic, is calculated with the following equation:
I
A × MC
The parameters in this equation are shown below:
MC
MC
MC
f
tog
A, B, C
CCINT
MAX
= 3.3 V ± 10% for commercial and industrial use.
LC
TON
DEV
USED
CCINT
INT
IO
=
TON
value, which depends on the device output load characteristics
+ P
= Number of macrocells with the Turbo Bit option turned on,
= Number of macrocells in the device
= Total number of macrocells in the design, as reported
= Highest clock frequency to the device
= Average ratio of logic cells toggling at each clock
= Constants, shown in
value, which depends on the switching frequency and the
IO
+ B × (MC
LAD
as reported in the MAX+PLUS II Report File (.rpt)
in the MAX+PLUS II Report File (.rpt)
(typically 0.125)
= I
, t
CC INT
LAC
MAX 7000 Programmable Logic Device Family Data Sheet
, t
IC
DEV
× V
, t
EN
– MC
CC
, t
SEXP
+ P
TON
, t
IO
ACL
Table 39
) + C × MC
MAX
, and t
in MHz) for MAX 7000 devices
CPPW
Table
Devices).
LAD
USED
parameters for macrocells
parameter into the signal
14. See
× f
MAX
Figure 13
× tog
LPA
parameter
for more
LC
53

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