IC MAX 7000 CPLD 64 84-PLCC

EPM7064SLC84-5

Manufacturer Part NumberEPM7064SLC84-5
DescriptionIC MAX 7000 CPLD 64 84-PLCC
ManufacturerAltera
SeriesMAX® 7000
EPM7064SLC84-5 datasheet
 

Specifications of EPM7064SLC84-5

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max5.0ns
Voltage Supply - Internal4.75 V ~ 5.25 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o68Operating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case84-PLCC
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Each programmable register can be clocked in three different modes:
By a global clock signal. This mode achieves the fastest clock-to-
output performance.
By a global clock signal and enabled by an active-high clock
enable. This mode provides an enable on each flipflop while still
achieving the fast clock-to-output performance of the global
clock.
By an array clock implemented with a product term. In this
mode, the flipflop can be clocked by signals from buried
macrocells or I/O pins.
In EPM7032, EPM7064, and EPM7096 devices, the global clock signal
is available from a dedicated clock pin, GCLK1, as shown in
In MAX 7000E and MAX 7000S devices, two global clock signals are
available. As shown in
Figure
true or the complement of either of the global clock pins, GCLK1 or
GCLK2.
Each register also supports asynchronous preset and clear functions.
As shown in
Figures 3
and 4, the product-term select matrix allocates
product terms to control these operations. Although the
product-term-driven preset and clear of the register are active high,
active-low control can be obtained by inverting the signal within the
logic array. In addition, each register clear function can be
individually driven by the active-low dedicated global clear pin
(GCLRn). Upon power-up, each register in the device will be set to a
low state.
All MAX 7000E and MAX 7000S I/O pins have a fast input path to a
macrocell register. This dedicated path allows a signal to bypass the
PIA and combinatorial logic and be driven to an input D flipflop with
an extremely fast (2.5 ns) input setup time.
Expander Product Terms
Although most logic functions can be implemented with the five
product terms available in each macrocell, the more complex logic
functions require additional product terms. Another macrocell can
be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel
expander product terms (“expanders”) that provide additional
product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.
2, these global clock signals can be the
Figure
1.
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