IC MAX 7000 CPLD 64 100-TQFP

EPM7064STI100-7N

Manufacturer Part NumberEPM7064STI100-7N
DescriptionIC MAX 7000 CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 7000
EPM7064STI100-7N datasheet
 


Specifications of EPM7064STI100-7N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max7.5ns
Voltage Supply - Internal4.5 V ~ 5.5 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o68Operating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-2315
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Page 19/66

Download datasheet (2Mb)Embed
PrevNext
The programming times described in
with the worst-case method using the enhanced ISP algorithm.
Table 6. MAX 7000S t
& Cycle
PULSE
Device
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Tables 7
verification times for several common test clock frequencies.
Table 7. MAX 7000S In-System Programming Times for Different Test Clock Frequencies
Device
10 MHz
5 MHz
EPM7032S
4.06
4.09
EPM7064S
4.55
4.60
EPM7128S
5.19
5.27
EPM7160S
5.45
5.55
EPM7192S
5.83
5.95
EPM7256S
6.59
6.75
Table 8. MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies
Device
10 MHz
5 MHz
EPM7032S
0.05
0.07
EPM7064S
0.06
0.09
EPM7128S
0.08
0.14
EPM7160S
0.09
0.16
EPM7192S
0.11
0.18
EPM7256S
0.13
0.24
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Values
TCK
Programming
t
(s)
Cycle
PPULSE
PTCK
4.02
342,000
4.50
504,000
5.11
832,000
5.35
1,001,000
5.71
1,192,000
6.43
1,603,000
and
8
show the in-system programming and stand alone
f
TCK
2 MHz
1 MHz
500 kHz
4.19
4.36
4.71
4.76
5.01
5.51
5.52
5.94
6.77
5.85
6.35
7.35
6.30
6.90
8.09
7.23
8.03
9.64
f
TCK
2 MHz
1 MHz
500 kHz
0.13
0.23
0.43
0.18
0.34
0.64
0.29
0.56
1.09
0.35
0.67
1.31
0.41
0.79
1.56
0.54
1.06
2.08
Tables 6
through
8
are associated
Stand-Alone Verification
t
(s)
Cycle
VPULSE
VTCK
0.03
200,000
0.03
308,000
0.03
528,000
0.03
640,000
0.03
764,000
0.03
1,024,000
200 kHz
100 kHz
50 kHz
5.73
7.44
10.86
7.02
9.54
14.58
9.27
13.43
21.75
10.35
15.36
25.37
11.67
17.63
29.55
14.45
22.46
38.49
200 kHz
100 kHz
50 kHz
1.03
2.03
4.03
1.57
3.11
6.19
2.67
5.31
10.59
3.23
6.43
12.83
3.85
7.67
15.31
5.15
10.27
20.51
Units
s
s
s
s
s
s
Units
s
s
s
s
s
s
19