EPM7064STI100-7N Altera, EPM7064STI100-7N Datasheet - Page 2

IC MAX 7000 CPLD 64 100-TQFP

EPM7064STI100-7N

Manufacturer Part Number
EPM7064STI100-7N
Description
IC MAX 7000 CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064STI100-7N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
68
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2315

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MAX 7000 Programmable Logic Device Family Data Sheet
...and More
Features
2
Usable gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
t
t
t
t
f
PD
SU
FSU
CO1
CNT
Table 2. MAX 7000S Device Features
Feature
(ns)
(ns)
(ns)
(MHz)
(ns)
EPM7032S
175.4
600
2.9
2.5
3.2
32
36
2
5
EPM7064S
Open-drain output option in MAX 7000S devices
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power-saving mode for a reduction of over 50% in
each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
Programmable security bit for protection of proprietary designs
3.3-V or 5.0-V operation
Enhanced features available in MAX 7000E and MAX 7000S devices
Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
1,250
175.4
2.9
2.5
3.2
64
68
4
5
MultiVolt
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
Six pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
Programmable output slew-rate control
EPM7128S
TM
2,500
147.1
128
100
I/O interface operation, allowing devices to
3.4
2.5
8
6
4
EPM7160S
3,200
149.3
160
104
3.4
2.5
3.9
10
6
EPM7192S
3,750
125.0
192
124
7.5
4.1
4.7
12
3
Altera Corporation
EPM7256S
5,000
128.2
256
164
7.5
3.9
4.7
16
3

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