IC MAX 7000 CPLD 64 100-TQFP

EPM7064STI100-7N

Manufacturer Part NumberEPM7064STI100-7N
DescriptionIC MAX 7000 CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 7000
EPM7064STI100-7N datasheet
 


Specifications of EPM7064STI100-7N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max7.5ns
Voltage Supply - Internal4.5 V ~ 5.5 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o68Operating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-2315
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MAX 7000 Programmable Logic Device Family Data Sheet
Figure 9
Figure 9. MAX 7000 JTAG Waveforms
Captured
Table 12
devices.
Symbol
f
For more information, see
Boundary-Scan Testing in Altera
24
shows the timing requirements for the JTAG signals.
TMS
TDI
t
JCP
t
t
JCH
JCL
TCK
t
JPZX
TDO
t
JSSU
Signal
to Be
t
JSZX
Signal
to Be
Driven
shows the JTAG timing parameters and values for MAX 7000S
Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices
Parameter
t
TCK clock period
JCP
t
TCK clock high time
JCH
t
TCK clock low time
JCL
t
JTAG port setup time
JPSU
t
JTAG port hold time
JPH
t
JTAG port clock to output
JPCO
t
JTAG port high impedance to valid output
JPZX
t
JTAG port valid output to high impedance
JPXZ
t
Capture register setup time
JSSU
t
Capture register hold time
JSH
t
Update register clock to output
JSCO
t
Update register high impedance to valid output
JSZX
t
Update register valid output to high impedance
JSXZ
Application Note 39 (IEEE 1149.1 (JTAG)
t
t
JPH
JPSU
t
JPCO
t
JSH
t
t
JSCO
JSXZ
Min
100
50
50
20
45
20
45
Devices).
Altera Corporation
t
JPXZ
Max
Unit
ns
ns
ns
ns
ns
25
ns
25
ns
25
ns
ns
ns
25
ns
25
ns
25
ns