EPM7064STI100-7N Altera, EPM7064STI100-7N Datasheet - Page 28

IC MAX 7000 CPLD 64 100-TQFP

EPM7064STI100-7N

Manufacturer Part Number
EPM7064STI100-7N
Description
IC MAX 7000 CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064STI100-7N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
68
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2315

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MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) The parameter is measured with 50% of the outputs each sourcing the specified current. The I
(11) The parameter is measured with 50% of the outputs each sinking the specified current. The I
(12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically
(13) Capacitance is measured at 25° C and is sample-tested only. The
Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices
Timing Model
28
Typical
Output
Current (mA)
See the
Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During transitions, the
inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than
20 ns.
Numbers in parentheses are for industrial-temperature-range devices.
V
The POR time for all 7000S devices does not exceed 300 μs. The sufficient V
device is fully initialized within the POR time after V
3.3-V I/O operation is not available for 44-pin packages.
The V
During in-system programming, the minimum DC input voltage is –0.3 V.
These values are specified under the MAX 7000 recommended operating conditions in
to high-level TTL or CMOS output current.
low-level TTL, PCI, or CMOS output current.
–60 μA.
CC
I
O
must rise monotonically.
CCISP
Operating Requirements for Altera Devices Data
150
120
90
60
30
parameter applies only to MAX 7000S devices.
1
V
O
2
Output Voltage (V)
Figure 11
devices.
MAX 7000 device timing can be analyzed with the Altera software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in
devices have fixed internal delays that enable the designer to determine
the worst-case timing of any design. The Altera software provides timing
simulation, point-to-point delay prediction, and detailed timing analysis
for a device-wide performance evaluation.
I
V
Room Temperature
I
3
OL
OH
CCIO
shows the typical output drive characteristics of MAX 7000
= 5.0 V
4
5
Sheet.
CCINT
Typical
Output
Current (mA)
reaches the sufficient POR voltage level.
I
O
OE1
pin has a maximum capacitance of 20 pF.
150
120
90
60
30
CCINT
1
voltage level for POR is 4.5 V. The
Figure
V
O
2
Output Voltage (V)
Table 14 on page
12. MAX 7000
V
Room Temperature
I
I
OL
OH
OL
3
C CIO
Altera Corporation
OH
3.3
parameter refers to
parameter refers
= 3.3 V
4
26.
5

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