IC MAX 7000 CPLD 64 100-TQFP

EPM7064STI100-7N

Manufacturer Part NumberEPM7064STI100-7N
DescriptionIC MAX 7000 CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 7000
EPM7064STI100-7N datasheet
 


Specifications of EPM7064STI100-7N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max7.5ns
Voltage Supply - Internal4.5 V ~ 5.5 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o68Operating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-2315
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MAX 7000 Programmable Logic Device Family Data Sheet
Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2)
Symbol
Parameter
t
Register clear time
CLR
t
PIA delay
PIA
t
Low-power adder
LPA
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in
information on switching waveforms.
(2)
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
(3)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4)
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5)
The f
values represent the highest frequency for pipelined data.
MAX
(6)
Operating conditions: V
CCIO
(7)
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8)
The t
parameter must be added to the t
LPA
running in the low-power mode.
Tables 35
Table 35. EPM7192S External Timing Parameters (Part 1 of 2)
Symbol
Parameter
t
Input to non-registered output
PD1
t
I/O input to non-registered
PD2
output
t
Global clock setup time
SU
t
Global clock hold time
H
t
Global clock setup time of fast
FSU
input
t
Global clock hold time of fast
FH
input
t
Global clock to output delay
CO1
t
Global clock high time
CH
t
Global clock low time
CL
t
Array clock setup time
ASU
48
Conditions
-6
Min Max Min Max Min Max Min Max
2.4
(7)
1.6
(8)
11.0
= 3.3 V ± 10% for commercial and industrial use.
, t
, t
, t
, t
LAD
LAC
IC
EN
SEXP
and
36
show the EPM7192S AC operating conditions.
Conditions
-7
Min
C1 = 35 pF
C1 = 35 pF
4.1
0.0
3.0
0.0
C1 = 35 pF
3.0
3.0
1.0
Note (1)
Speed Grade
-7
-10
-15
3.0
3.0
2.0
1.0
10.0
11.0
Table
14. See
Figure 13
parameter into the signal
LAD
, t
, and t
parameters for macrocells
ACL
CPPW
Note (1)
Speed Grade
-10
-15
Max
Min
Max
Min
7.5
10.0
7.5
10.0
7.0
11.0
0.0
0.0
3.0
3.0
0.5
0.0
4.7
5.0
4.0
5.0
4.0
5.0
2.0
4.0
Altera Corporation
Unit
4.0
ns
2.0
ns
13.0
ns
for more
parameter
LPA
Unit
Max
15.0
ns
15.0
ns
ns
ns
ns
ns
8.0
ns
ns
ns
ns