IC MAX 7000 CPLD 64 100-TQFP

EPM7064STI100-7N

Manufacturer Part NumberEPM7064STI100-7N
DescriptionIC MAX 7000 CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 7000
EPM7064STI100-7N datasheet
 


Specifications of EPM7064STI100-7N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max7.5ns
Voltage Supply - Internal4.5 V ~ 5.5 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o68Operating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-2315
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MAX 7000 Programmable Logic Device Family Data Sheet
MAX 7000 devices contain from 32 to 256 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
The MAX 7000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
designer to configure one or more macrocells to operate at 50% or lower
power while adding only a nominal timing delay. MAX 7000E and
MAX 7000S devices also provide an option that reduces the slew rate of
the output buffers, minimizing noise transients when non-speed-critical
signals are switching. The output drivers of all MAX 7000 devices (except
44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing
MAX 7000 devices to be used in mixed-voltage systems.
The MAX 7000 family is supported byAltera development systems, which
are integrated packages that offer schematic, text—including VHDL,
Verilog HDL, and the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The software runs
on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series
700/800 workstations.
f
For more information on development tools, see the
Programmable Logic Development System & Software Data Sheet
Quartus Programmable Logic Development System & Software Data
Functional
The MAX 7000 architecture includes the following elements:
Description
6
Logic array blocks
Macrocells
Expander product terms (shareable and parallel)
Programmable interconnect array
I/O control blocks
MAX+PLUS II
and the
Sheet.
Altera Corporation