XC9536XL-5VQ44C Xilinx Inc, XC9536XL-5VQ44C Datasheet

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XC9536XL-5VQ44C

Manufacturer Part Number
XC9536XL-5VQ44C
Description
IC CPLD 36 MCELL 3.3V 44-VQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr
Datasheet

Specifications of XC9536XL-5VQ44C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
5.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
36
Number Of Gates
800
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
122-1259
XC9536XL-5VQ44C

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XC9536XL-5VQ44C
Manufacturer:
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Quantity:
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Part Number:
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DS058 (v1.9) April 3, 2007
Features
WARNING: Programming temperature range of
T
Description
The XC9536XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two
DS058 (v1.9) April 3, 2007
Product Specification
A
= 0° C to +70° C
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
36 macrocells with 800 usable gates
Available in small footprint packages
-
-
-
-
-
Optimized for high-performance 3.3V systems
-
-
-
-
Advanced system features
-
-
-
-
-
-
-
-
-
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
-
-
Pin-compatible with 5V-core XC9536 device in the
44-pin PLCC package and the 48-pin CSP package
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
44-pin PLCC (34 user I/O pins)
44-pin VQFP (34 user I/O pins)
48-pin CSP (36 user I/O pins)
64-pin VQFP (36 user I/O pins)
Pb-free available for all packages
Low power operation
5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V
signals
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
In-system programmable
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Endurance exceeding 10,000 program/erase
cycles
20 year data retention
ESD protection exceeding 2,000V
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
0
XC9536XL High Performance
CPLD
Product Specification
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
used:
I
where:
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
value varies with the design application and should be veri-
fied during normal system operation.
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
CC
(mA) = MC
MC
PT
per macrocell
MC
PT
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
HS
LP
HS
LP
+ 0.272) + 0.04 * MC
= average number of low power product terms per
= average number of high-speed product terms
= # macrocells in low power configuration
= # macrocells in high-speed configuration
HS
(0.175*PT
CC
HS
, the following equation may be
TOG
+ 0.345) + MC
(MC
Figure 2
HS
Figure 1
+MC
for architecture
LP
LP
(0.052*PT
)* f
shows the
LP
CC
1

Related parts for XC9536XL-5VQ44C

XC9536XL-5VQ44C Summary of contents

Page 1

... C to +70° Description The XC9536XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of two © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... I/O/GCK 1 I/O/GSR 2 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 178 MHz 200 250 DS058_01_121501 JTAG Controller I/O Blocks Figure 2: XC9536XL Architecture www.xilinx.com In-System Programming Controller 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells DS058_02_081500 DS058 (v1.9) April 3, 2007 ...

Page 3

... Max; CC CCIO V = GND or 3. Min < V < 5. GND 1.0 MHz GND, No load 1.0 MHz IN www.xilinx.com XC9536XL High Performance CPLD Value –0.5 to 4.0 –0.5 to 5.5 –0.5 to 5.5 –65 to +150 +150 by 4.0V. CCINT information on the Xilinx website. For Pb-free Min Max 3.0 3.6 o ...

Page 4

... XC9536XL High Performance CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input PSU T I/O hold time after p-term clock input ...

Page 5

... Internal low power logic delay LOGILP Feedback Delays T Fast CONNECT II feedback delay F Time Adders T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW DS058 (v1.9) April 3, 2007 Product Specification XC9536XL High Performance CPLD XC9536XL-5 XC9536XL-7 Min Max Min Max - 1.5 - 2.3 - 1 ...

Page 6

... Notes: 1. Global control pin. 2. The pin-outs are the same for Pb-free versions of packages. XC9536XL Global, JTAG and Power Pins Pin Type PC44 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS V 3.3V 21, 41 CCINT V 2.5V/3.3V CCIO GND 10, 23 Connects Notes: 1 ...

Page 7

... Line 3 = Not related to device part number. · Line 4 = Package code, speed, operating temperature, three digits not related to part number. Package codes CS48 CSG48. Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC9536XL-5PC44C 5 ns XC9536XL-5VQ44C 5 ns XC9536XL-5CS48C 5 ns XC9536XL-5VQ64C 5 ns XC9536XL-7PC44C 7.5 ns XC9536XL-7VQ44C 7.5 ns XC9536XL-7CS48C 7 ...

Page 8

... Quad Flat Pack (VQFP); Pb-free CSG48 48-ball Chip Scale Package (CSP); Pb-free VQG64 64-pin Quad Flat Pack (VQFP); Pb-free = –40° to +85°C. A Pb- Free Example: XC9536XL 144 C Device Speed Grade Package Type Pb -Free Number of Pins Temperature Range www.xilinx.com Operating ...

Page 9

... DS058 (v1.9) April 3, 2007 Product Specification Revision equation, page 1. Removed -4 device. Added industrial availability test conditions and measurements to DC Characteristics table from 260 to 220 C. Added Device Part Marking and updated Ordering SOL specification to AC Characteristics. APRPW www.xilinx.com XC9536XL High Performance CPLD 9 ...

Page 10

... XC9536XL High Performance CPLD 10 www.xilinx.com R DS058 (v1.9) April 3, 2007 Product Specification ...

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