XC9536-6PC44C

Manufacturer Part NumberXC9536-6PC44C
DescriptionIC CPLD 36 MCELL C-TEMP 44-PLCC
ManufacturerXilinx Inc
SeriesXC9500
XC9536-6PC44C datasheets

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Specifications of XC9536-6PC44C

Programmable TypeIn System Programmable (min 10K program/erase cycles)Delay Time Tpd(1) Max6.0ns
Voltage Supply - Internal4.75 V ~ 5.25 VNumber Of Logic Elements/blocks2
Number Of Macrocells36Number Of Gates800
Number Of I /o34Operating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case44-PLCC
Voltage5VMemory TypeFLASH
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantFeatures-
Number Of Logic Elements/cells-Other names122-1253
XC9536-6PC44C
XC9536-15PCG44C PDF datasheetXC9536-15PCG44C PDF datasheet #2
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DS064 (v6.3) April 3, 2006
Features
•
5 ns pin-to-pin logic delays on all pins
•
f
to 100 MHz
CNT
•
36 macrocells with 800 usable gates
•
Up to 34 user I/O pins
•
5V in-system programmable
-
Endurance of 10,000 program/erase cycles
-
Program/erase over full commercial voltage and
temperature range
•
Enhanced pin-locking architecture
•
Flexible 36V18 Function Block
-
90 product terms drive any or all of 18 macrocells
within Function Block
-
Global and product term clocks, output enables,
set and reset signals
•
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
•
Programmable power reduction mode in each
macrocell
•
Slew rate control on individual outputs
•
User programmable ground pin capability
•
Extended pattern security features for design
protection
•
High-drive 24 mA outputs
•
3.3V or 5V I/O capability
•
Advanced CMOS 5V FastFLASH™ technology
•
Supports parallel programming of more than one
XC9500 concurrently
•
Available in 44-pin PLCC, 44-pin VQFP, 48-pin CSP
packages
© 1996-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS064 (v6.3) April 3, 2006
Product Specification
0
XC9536 In-System
Programmable CPLD
Product Specification
0
5
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See
overview.
Power Management
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
(mA) = MC
(1.7) + MC
CC
HP
Where:
MC
= Macrocells in high-performance mode
HP
MC
= Macrocells in low-power mode
LP
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
shows a typical calculation for the XC9536 device.
(50)
(30)
0
Clock Frequency (MHz)
Figure 1: Typical I
CC
www.xilinx.com
Figure 2
for the architecture
(0.9) + MC (0.006 mA/MHz) f
LP
(83)
(50)
50
100
DS064_01_110101
vs. Frequency for XC9536
1

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XC9536-6PC44C Summary of contents

  • Page 1

    ... Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See overview. Power Management Power dissipation can be reduced in the XC9536 by config- uring macrocells to standard or low-power modes of opera- tion. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for ...

  • Page 2

    ... I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC9536 Architecture www.xilinx.com 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells DS064_02_110101 DS064 (v6.3) April 3, 2006 Product Specification ...

  • Page 3

    ... –3 Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz www.xilinx.com XC9536 In-System Programmable CPLD Value –0.5 to 7.0 –0 0.5 CC –0 0.5 CC –65 to +150 +150 Min Max o C 4.75 5. 4.5 5 4.75 5. 4.5 5.5 3.0 3.6 0 0.80 2 0.5 CCINT ...

  • Page 4

    ... XC9536 In-System Programmable CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO (1) f 16-bit counter frequency CNT (2) f Multiple FB internal operating SYSTEM frequency T I/O setup time before p-term ...

  • Page 5

    ... SLEW Notes multiplied by the span of the function as defined in the XC9500 family data sheet. PTA DS064 (v6.3) April 3, 2006 Product Specification XC9536 In-System Programmable CPLD XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min Max - 1 ...

  • Page 6

    ... Notes Global control pin. XC9536 Global, JTAG and Power Pins Pin Type PC44 I/O/GCK1 5 I/O/GCK2 6 I/O/GCK3 7 I/O/GTS1 42 I/O/GTS2 40 I/O/GSR 39 TCK 17 TDI 15 TDO 30 TMS 21, 41 CCINT V 3.3V/5V 32 CCIO GND 23, 10 Connects — 6 BSca n Function CS48 Order Block 40 D6 105 2 41 ...

  • Page 7

    ... Package code CS48. Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC9536-5PC44C 5 ns XC9536-5PCG44C 5 ns XC9536-5VQ44C 5 ns XC9536-5VQG44C 5 ns XC9536-5CS48C 5 ns XC9536-5CSG48C 5 ns XC9536-6PC44C 6 ns XC9536-6PCG44C 6 ns XC9536-6VQ44C 6 ns XC9536-6VQG44C 6 ns XC9536-7PC44C 7.5 ns XC9536-7PCG44C 7.5 ns XC9536-7VQ44C 7.5 ns XC9536-7VQG44C 7.5 ns XC9536-7CS48C 7.5 ns XC9536-7CSG48C 7 ...

  • Page 8

    ... XC9536 In-System Programmable CPLD Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC9536-10VQG44C 10 ns XC9536-10CS48C 10 ns XC9536-10CSG48C 10 ns XC9536-10PC44I 10 ns XC9536-10PCG44I 10 ns XC9536-10VQ44I 10 ns XC9536-10VQG44I 10 ns XC9536-10CS48I 10 ns XC9536-10CSG48I 10 ns XC9536-15PC44C 15 ns XC9536-15PCG44C 15 ns XC9536-15VQ44C 15 ns XC9536-15VQG44C 15 ns XC9536-15PC44I 15 ns ...

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