CY7C373I-100JC Cypress Semiconductor Corp, CY7C373I-100JC Datasheet
CY7C373I-100JC
Specifications of CY7C373I-100JC
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CY7C373I-100JC Summary of contents
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... V 3.3IO Cypress Semiconductor Corporation Document #: 38-03030 Rev. ** UltraLogic™ 64-Macrocell Flash CPLD Functional Description The CY7C373i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the F 370i™ family of high-density, high-speed CPLDs. Like LASH all members of the F ...
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... GND I/O /SDI I/O 48 CLK / GND CCIO CLK / I I 7C373i– SDI 74 V CCIO 73 I I I CLK / GND CCIO CLK / GND 7C373i– CY7C373i Page ...
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... I/O pin is used as an input. Document #: 38-03030 Rev. ** Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C373i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. ...
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... Max 0.5V CC OUT V = Max mA, CC OUT MHz GND Min 0. Min 2. Max Max CCINT CY7C373i Ambient V CC Temperature V CCINT + 0.25V + 0.5V Min. Typ. [3] 2.4 [3, 4] [3, 4] [3] [5] 2.0 [5] –0.5 –10 –50 [4] 0 –70 –30 Com’l/Ind. 75 Com’l “L”, –66 45 +75 – ...
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... Output Waveform–Measurement Level V OH 0. 0.5V (d) Test Waveforms EN measured with 35-pF AC Test Load. EA Min. Max 100-Pin TQFP 84-Lead PLCC 8 8 Max. 100 ALL INPUT PULSES 3.0V 90% 10% GND < ( Max. CY7C373i Unit pF pF Unit nH Unit Cycles 90% 10% < 7C373i–5 Page ...
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... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 12. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C373i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...
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... CLOCK REGISTERED OUTPUT CLOCK Document #: 38-03030 Rev (continued) 7C373i–125 Min. Max. 8 125 + t ), 1/( [7] 10 [7] 12 [1] 16 [7] 10 [7] 12 [1] 16 500 CY7C373i 7C373i–83 7C373i–66 7C373i–100 7C373iL-83 7C373iL–66 Min. Max. Min. Max. Min 83.3 66.6 50 500 500 500 ...
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... LATCH ENABLE LATCHED OUTPUT Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Document #: 38-03030 Rev PDL t ICS PDL t WH CY7C373i SCS t ICO t WL Page 7C373i–8 7C373i–10 7C373i–11 ...
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... Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Document #: 38-03030 Rev ICOL t ICS CY7C373i t PDLL 7C373i– 7C373i– 7C373i–14 Page ...
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... CY7C373i–100AI CY7C373i–100JI 83 CY7C373i–83AC CY7C373i–83JC CY7C373i–83AI CY7C373i–83JI CY7C373iL–83JC 66 CY7C373i–66AC CY7C373i–66JC CY7C373i–66AI CY7C373i–66JI CY7C373iL–66JC F 370, F 370i, ISR, UltraLogic, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor LASH LASH Corporation. ...
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... Package Diagrams Document #: 38-03030 Rev. ** 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 CY7C373i 51-85048-B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Lead Plastic Leaded Chip Carrier J83 CY7C373i 51-85006-A Page ...
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... Document Title: CY7C373i UltraLogic™ 64-Macrocell Flash CPLD Document Number: 38-03030 Issue REV. ECN NO. Date ** 106375 09/17/01 Document #: 38-03030 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00495 to 38-03030 CY7C373i Page ...