CY37128P100-125AXI Cypress Semiconductor Corp, CY37128P100-125AXI Datasheet
CY37128P100-125AXI
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CY37128P100-125AXI Summary of contents
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... Pb-free packages available ❐ Note 1. Due to the 5V tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V Cypress Semiconductor Corporation Document Number : 38-03007 Rev and 3.3 V ISR™ High Performance General Description The Ultra37000™ family of CMOS CPLDs provides a range of high density programmable logic solutions with unparalleled system performance ...
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Contents Features ............................................................................. 1 General Description ......................................................... 1 Ultra37000 5V Devices ................................................ 1 Ultra37000V 3.3V Devices .......................................... 1 Contents ............................................................................ 2 Selection Guide ................................................................ 3 5V Selection Guide ...................................................... 3 3.3V Selection Guide ................................................... 3 Architecture Overview of Ultra37000 Family ...
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Selection Guide 5 V Selection Guide Table 1. General Information Device Macrocells Dedicated Inputs CY37032 32 CY37064 64 CY37128 128 CY37192 192 CY37256 256 Table 2. Speed Bins Device 200 CY37032 CY37064 X CY37128 CY37192 CY37256 Table 3. Device-Package Offering ...
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Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations. ...
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Low Power Option Each logic block can operate in high speed mode for critical path performance low power mode for power conservation. The logic block mode is set by the user on a logic block by logic block ...
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FROM PTM PRODUCT TERMS FROM PTM PRODUCT TERMS C24 ASYNCHRONOUS BLOCK RESET 4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3) ASYNCHRONOUS 1 ASYNCHRONOUS CLOCK(PTCLK) ...
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INPUT/CLOCK PIN D 0 FROM CLOCK 1 O POLARITY INPUT 2 CLOCK PINS Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) and an asynchronous product term ...
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JTAG and PCI Standards PCI Compliance 5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, ...
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The second method for programming Ultra37000 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information. The third programming option for ...
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Logic Block Diagrams CY37032/CY37032V 16 I/Os I/O I CY37064/CY37064V 16 I/Os I/O -I I/Os I/O -I TDI JTAG Tap TCK TDO Controller TMS Document Number : 38-03007 Rev. *H Clock/ Input Input 4 ...
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Logic Block Diagrams (continued) CY37128/CY37128V 16 I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I CY37192/CY37192V 10 I/Os I/O –I I/Os I/O –I/O ...
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Logic Block Diagrams (continued) CY37256/CY37256V 12 I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I/O 60 ...
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Device Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage to Ground ...
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Inductance [5] Parameter Description L Maximum Pin Inductance Capacitance [5] Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK [9] C Dual-Function Pins DP Endurance Characteristics [5] Parameter Description N Minimum Reprogramming Cycles 3.3V Device Maximum Ratings Exceeding ...
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Inductance [5] Parameter Description L Maximum Pin Inductance Capacitance [5] Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK [9] C Dual Functional Pins DP Endurance Characteristics [5] Parameter Description N Minimum Reprogramming Cycles AC Characteristics Figure 7. ...
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Parameter V t 1.5V ER(–) t 2.6V ER(+) t 1.5V EA(+) t V EA(–) Switching Characteristics [12] Over the Operating Range Parameter Combinatorial Mode Parameters [13, 14, 15] t Input to Combinatorial Output PD [13, 14, 15] t Input ...
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Switching Characteristics [12] Over the Operating Range (continued) Parameter Product Term Clocking Parameters [13, 14, 15] t Product Term Clock or Latch Enable (PTCLK) to Output COPT t Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ...
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Switching Characteristics [12] Over the Operating Range 200 MHz 167 MHz 154 MHz Parameter Combinatorial Mode Parameters [13, 14, 15 6.5 PD [13, 14, 15 12.5 PDL [13, 14, 15 13.5 PDLL [13, 14, ...
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Switching Characteristics [12] Over the Operating Range (continued) 200 MHz 167 MHz 154 MHz Parameter [13, 14, 15 [13 [13, 14, 15 User ...
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Switching Waveforms (continued) Figure 11. Registered Output with Product Term Clocking Input Going Through the Array INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Figure 12. Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT PRODUCT TERM CLOCK ...
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Switching Waveforms (continued) REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK LATCHED INPUT LATCH ENABLE t COMBINATORIAL OUTPUT LATCH ENABLE Document Number : 38-03007 Rev. *H Figure 14. Registered Input ICO ...
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Switching Waveforms (continued) LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE INPUT REGISTERED OUTPUT CLOCK Document Number : 38-03007 Rev. *H Figure 17. Latched Input and Output t ICOL t ICS Figure ...
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Switching Waveforms (continued) INPUT REGISTERED OUTPUT CLOCK INPUT OUTPUTS Power Consumption Typical 5V Power Consumption CY37032 The typical pattern is a 16-bit up counter, ...
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Typical 5V Power Consumption (continued) CY37064 The typical pattern is a 16-bit up counter, per logic block, with ...
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Typical 5V Power Consumption (continued) CY37192 The typical pattern is a 16-bit up counter, per logic block, with outputs ...
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Typical 3.3V Power Consumption CY37032V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37064V ...
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Typical 3.3V Power Consumption (continued) CY37128V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. ...
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Typical 3.3V Power Consumption (continued) CY37256V The typical pattern is a 16-bit up counter, per logic block, with outputs ...
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Pin Configurations [20] I/O /TCK 5 I/O I/O CLK 2 JTAG EN GND CLK /I 0 I/O I/O I/O I/O I/O /TCK 5 CLK JTAG GND CLK I/O I/O I/O Notes 20. For 3.3V versions (Ultra37000V ...
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Pin Configurations [20] (continued) 100 TCK 1 GND CLK / ...
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Pin Configurations [20] (continued) GND I I/O /TCK I GND 10 11 I I/O ...
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Pin Configurations [20] (continued) GND I I TCK 6 7 I GND 10 11 I ...
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Pin Configurations [20] (continued I/O I I/O I/O I I/O I ...
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... Macrocells Speed Ordering Code (MHz) 32 154 CY37032P44-154AXI 125 CY37032P44-125AXC CY37032P44-125JXC 64 125 CY37064P44-125AXC CY37064P44-125JXC CY37064P100-125AXC CY37064P44-125AXI CY37064P100-125AXI 128 125 CY37128P100-125AXC CY37128P160-125AXC CY37128P100-125AXI CY37128P160-125AXI 100 CY37128P160-100AXC 192 83 CY37192P160-83AXC CY37192P160-83AXI 256 125 CY37256P160-125AXC CY37256P160-125AXI 83 CY37256P160-83AXC CY37256P160-83AXI 3.3 V Ordering Information Speed Macrocells (MHz) Ordering Code ...
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Ordering Code Definitions 128 V P 100 - 125 Cypress Semiconductor ID Family Type 37 = Ultra37000 Family Macrocell Density Macrocells 192 = 192 Macrocells Macrocells 256 ...
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Package Diagrams Figure 21. 44-Pin Pb-free Thin Plastic Quad Flat Pack A44 Figure 22. 44-Pin Pb-free Plastic Leaded Chip Carrier J67 Document Number : 38-03007 Rev. *H Ultra37000 CPLD Family 51-85064 *D 51-85003-*B Page [+] Feedback ...
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Figure 23. 100-Pin Pb-free Thin Plastic Quad Flat Pack (TQFP) A100 Document Number : 38-03007 Rev. *H Ultra37000 CPLD Family 51-85048 *D Page [+] Feedback ...
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Figure 24. 160-Pin Pb-free Thin Plastic Quad Flat Pack ( 1.4 mm) (TQFP) A160 Document Number : 38-03007 Rev. *H Ultra37000 CPLD Family 51-85049 *C Page [+] Feedback ...
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Document Number : 38-03007 Rev. *H Figure 25. 256-Ball FBGA ( mm) BB256 Ultra37000 CPLD Family 51-85108 *H Page [+] Feedback ...
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... CY37032P44-200AXC, CY37032P44-200JXC, CY37032P44-154AXI, CY37032P44-154JXI, CY37032P44-125AXC, CY37032P44-125JXC, CY37064P44-200AXC, CY37064P44-200JXC, CY37064P100-200AXC, CY37064P44-154AXI, CY37064P44-154JXI, CY37064P44-125AXC, CY37064P44-125JXC, CY37064P100-125AXC, CY37064P44-125AXI, CY37064P100-125AXI, CY37128P84-167JXC, CY37128P100-167AXC, CY37128P160-167AXC, CY37128P84-125JXC, CY37128P100-125AXC, CY37128P160-125AXC, CY37128P84-125JXI, CY37128P100-125AXI, CY37128P160-125AXI, CY37128P84-100JXC, CY37128P100-100AXC, CY37128P160-100AXC, CY37128P100-100AXI, CY37192P160-154AXC, CY37192P160-125AXC, CY37192P160-125AXI, CY37192P160-83AXC, CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC, CY37256P160-125AXI, CY37256P160-83AXC, CY37256P160-83AXI, CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI, ...
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... CY37064P100-125AI, 5962-9951901QYA, CY37128P84-167JC, CY37128P84-167JXC, CY37128P100-167AC, CY37128P100-167AXC, CY37128P160-167AC, CY37128P84-125JC, CY37128P84-125JXC, CY37128P100-125AC, CY37128P160-125AC, CY37128P84-125JI, CY37128P84-125JXI, CY37128P100-125AI, CY37128P160-125AI, 5962-9952102QYA, CY37128P84-100JC, CY37128P84-100JXC, CY37128P100-100AC, CY37128P160-100AC, CY37128P84-100JI, CY37128P100-100AI, CY37128P100-100AXI, CY37128P160-100AI, 5962-9952101QYA, CY37192P160-154AC, CY37192P160-154AXC, CY37192P160-125AC, CY37192P160-125AI, CY37192P160-83AC, CY37192P160-83AI, CY37256P160-154AC, CY37256P160-154AXC, CY37256P208-154NC, CY37256P256-154BGC, CY37256P160-125AC, CY37256P208-125NC, CY37256P256-125BGC, CY37256P160-125AI, CY37256P208-125NI, CY37256P256-125BGI, 5962-9952302QZC, ...
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Document Title: Ultra37000 CPLD Family 5 V and 3.3 V ISR™ High Performance CPLDs Document Number: 38-03007 Submission Orig. of Rev. ECN No. Date Change *G 2896152 03/19/2010 AAE *H 3081920 11/09/2010 AAE Document Number : 38-03007 Rev. *H Description ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...