CY37128P100-125AXIT Cypress Semiconductor Corp, CY37128P100-125AXIT Datasheet - Page 5

• Manufacturer Part Number: CY37128P100-125AXIT
• Description: IC CPLD 128 MACROCELL 100-LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37128P100-125AXIT

• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Macrocells: 128
• Number Of I /o: 69
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Features: Programmable
• Voltage: 5V
• Memory Type: CMOS
• For Use With: CY3710 - ADAPTER SOCKET PTG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

Document #: 38-03007 Rev. *E
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
FROM PTM
PRODUCT
FROM PTM
PRODUCT
TERMS
TERMS
0
0
−
−
ASYNCHRONOUS
16
16
BLOCK RESET
ASYNCHRONOUS
BLOCK PRESET
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
4
4
C0 C1 C24
0
1
2
3
C0
0
1
2
3
C1
C24
O
Q
Figure 2. I/O and Buried Macrocells
C25
C25
0
1
1
0
0
1
1
0
BURIED MACROCELL
0
1
I/O MACROCELL
C7
D/T/L
O
R
P
FEEDBACK TO PIM
Q
FEEDBACK TO PIM
FEEDBACK TO PIM
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in
bus-interface applications. Bus-hold additionally allows
unused device pins to remain unconnected on the board,
which is particularly useful during prototyping as designers can
route new signals to the device without cutting trace connec-
tions to V
note Understanding Bus-Hold—A Feature of Cypress CPLDs.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
D/T/L
DECODE
C2 C3
0
1
P
R
Q
O
CC
DECODE
C2 C3
0
1
or GND. For more information, see the application
O
Ultra37000 CPLD Family
0
1
C4
O
SLOW
“0”
“1”
FAST
OE0 OE1
0
1
2
3
SLEW
C6 C5
C26
O
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I/O CELL