ADSP-2105BPZ-80 Analog Devices Inc, ADSP-2105BPZ-80 Datasheet - Page 47

IC DSP CONTROLLER 16BIT 68PLCC

ADSP-2105BPZ-80

Manufacturer Part Number
ADSP-2105BPZ-80
Description
IC DSP CONTROLLER 16BIT 68PLCC
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2105BPZ-80

Interface
Synchronous Serial Port (SSP)
Clock Rate
20MHz
Non-volatile Memory
External
On-chip Ram
3kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
No. Of Bits
16
Frequency
20MHz
Core Supply Voltage
5.5V
No. Of Mips
25
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
PLCC
Embedded Interface Type
Host Port
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-2105BPZ-80
Manufacturer:
IDT
Quantity:
101
Part Number:
ADSP-2105BPZ-80
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-2105BPZ-80
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADSP-2105BPZ-80
Quantity:
540
REV. B
TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQUEST/GRANT
Parameter
Timing Requirement:
t
t
Switching Characteristic:
t
t
t
t
NOTES
1
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
requires a pulse width greater than 10 ns.
If BR meets the t
BH
BS
SD
SDB
SE
SEC
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR Disable to BG Low
BG High to DMS, PMS, BMS, RD, WR Enable
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
BS
and t
BH
PMS, DMS
BMS, RD
CLKOUT
CLKOUT
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
WR
BG
BR
t
1
SD
t
BH
1
t
BS
t
SDB
Figure 41. Bus Request/Grant
–47–
10.24 MHz
Min
29.4
44.4
0
0
14.4
Max
44.4
t
SE
t
SEC
Frequency
Dependency
Min
0.25t
0.25t
0.25t
CK
CK
CK
+ 5
+ 20
– 10
Max
0.25t
ADSP-21xx
CK
+ 20
Unit
ns
ns
ns
ns
ns
ns

Related parts for ADSP-2105BPZ-80