ADSP-2105BPZ-80 Analog Devices Inc, ADSP-2105BPZ-80 Datasheet - Page 5

• Manufacturer Part Number: ADSP-2105BPZ-80
• Description: IC DSP CONTROLLER 16BIT 68PLCC
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2105BPZ-80

• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: External
• On-chip Ram: 3kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• No. Of Bits: 16
• Frequency: 20MHz
• Core Supply Voltage: 5.5V
• No. Of Mips: 25
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• Embedded Interface Type: Host Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. B
One bus grant execution mode (GO Mode) allows the ADSP-
21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-21xx processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. There is also a master RESET signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. The ADSP-2111 has three
additional flag outputs whose states are controlled through
software.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
GENERATOR
ADDRESS
OUTPUT REGS
DATA
INPUT REGS
#1
ALU
16
24
GENERATOR
ADDRESS
DMD BUS
DATA
PMD BUS
#2
OUTPUT REGS
14
14
INPUT REGS
PMA BUS
DMA BUS
MAC
INSTRUCTION
SEQUENCER
PROGRAM
REGISTER
Figure 1. ADSP-21xx Block Diagram
OUTPUT REGS
INPUT REGS
SHIFTER
EXCHANGE
R Bus
16
BUS
PROGRAM
MEMORY
or ROM
SRAM
(Not on ADSP-2105)
TRANSMIT REG
RECEIVE REG
–5–
24
SERIAL
PORT 0
5
Serial Ports
The ADSP-21xx processors include two synchronous serial
ports (“SPORTs”) for serial communications and multiproces-
sor communication. All of the ADSP-21xx processors have two
serial ports (SPORT0, SPORT1) except for the ADSP-2105,
which has only SPORT1.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
SCLK
RFS
TFS
DR
DT
The ADSP-21xx serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
MEMORY
SRAM
DATA
16
COMPANDING
CIRCUITRY
PMD BUS
PMA BUS
DMA BUS
DMD BUS
Function
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
TRANSMIT REG
RECEIVE REG
GENERATOR
ADDRESS
SERIAL
PORT 1
5
BOOT
(ADSP-2111 Only)
TIMER
FLAGS
HOST INTERFACE PORT
(ADSP-2111 Only)
ADSP-21xx
MUX
MUX
CONTROL
HOST
PORT
HOST
PORT
DATA
3
14
24
HOST PORT
EXTERNAL
11
16
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BUS