ADSP-2101BPZ-100 Analog Devices Inc, ADSP-2101BPZ-100 Datasheet - Page 14

• Manufacturer Part Number: ADSP-2101BPZ-100
• Description: IC DSP SLG 16BIT 25MHZ 68-PLCC
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2101BPZ-100

• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 25MHz
• Non-volatile Memory: External
• On-chip Ram: 6kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• No. Of Bits: 16
• Frequency: 25MHz
• Core Supply Voltage: 5.5V
• No. Of Mips: 25
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• Embedded Interface Type: Host Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21xx
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
–14–
Functional Differences for Older Revision Devices
Older revisions of the ADSP-21xx processors have slight
differences in functionality. The two differences are as follows:
•
•
To determine the revision of a particular ADSP-21xx device,
inspect the marking on the device. For example, an ADSP-2101
of revision 6.0 will have the following marking:
The revision codes for the older versions of each ADSP-21xx
device are as follows:
Processor
ADSP-2101
ADSP-2105
ADSP-2115
ADSP-2111
ADSP-2103
Bus Grant (BG) is asserted in the same cycle that Bus
Request (BR) is recognized (i.e. when setup and hold time
requirements are met for the BR input). Bus Request input is
a synchronous input rather than asynchronous. (In newer
revision devices, BG is asserted in the cycle after BR is
recognized.)
Only the standard IDLE instruction is available, not the
clock-reducing IDLE n instruction.
Old Functionality
Revision Code 5.0
No Revision Code
Revision Code < 1.0
RevisionCode < 2.0
Revision code 5.0
EE/A12345-6.0
ADSP-2101
a
KS-66
9234
New Functionality
Revision Code
Revision Code
Revision Code 1.0
Revision Code 2.0
Revision code
Package & Speed
Lot # & Revision Code
Date Code
REV. B
6.0
6.0
1.0