ADSP-21061KS-133 Analog Devices Inc, ADSP-21061KS-133 Datasheet
ADSP-21061KS-133
Specifications of ADSP-21061KS-133
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ADSP-21061KS-133 Summary of contents
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... STATUS AND DATA BUFFERS Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel : 781.329.4700 Fax: 781.461.3113 Commercial Grade Family DSP Microcomputer ADSP-21061/ADSP-21061L For more information, see Ordering JTAG TEST AND EMULATION I/O PORT ADDR DATA DATA ...
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... Off-Chip Memory Interfacing 4 gigawords addressable Programmable wait state generation, page-mode DRAM support DMA Controller 6 DMA channels for transfers between ADSP-21061 internal memory and external memory, external peripherals, host processor, or serial ports Background DMA transfers MHz, in parallel with full-speed processor execution Host Processor Interface to 16- and 32-Bit ...
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... Ordering Guide ......................................................53 GENERAL NOTE This data sheet represents production released specifications for the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for 33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The product name“ADSP-21061” is used throughout this data sheet to represent all devices, except where expressly noted. ...
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... SRAM and integrated I/O peripherals supported by a dedicated I/O bus. Fabricated in a high speed, low power CMOS process, the ADSP-21061 has instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. ...
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... Figure 4 for the ADSP-21061 memory map). On the ADSP-21061, the memory can be configured as a maxi- mum of 32k words of 32-bit data, 64k words for 16-bit data, 16k words of 48-bit instructions (and 40-bit data) or combinations of different word sizes megabit. All the memory can be accessed as 16-bit, 32-bit, or 48-bit ...
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... BUS PRIORITY RESET CLOCK DMA transfers can occur between the ADSP-21061’s internal memory and either external memory, external peripherals host processor. DMA transfers can also occur between the ADSP-21061’s internal memory and its serial ports. ADSP-21061 #6 ADSP-21061 #5 ADSP-21061 #4 ADSP-21061 #3 ADDR31– ...
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... A vec- tor interrupt is provided for interprocessor commands. Maxi- mum throughput for interprocessor data transfer is 500 Mbps over the external port. Broadcast writes allow simultaneous transmission of data to all ADSP-21061s and can be used to implement reflective semaphores. ADDRESS 0x0000 0000 ...
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... If you develop your application using the ADSP-21062, but will migrate to the ADSP-21061, use only the first eight columns of each memory bank. Limit your application instructions 16k of data in each bank of the ADSP-21062, or any combination of instructions or data that does not exceed the memory bank. ...
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... ADDITIONAL INFORMATION ®† evaluation plat- This data sheet provides a general overview of the ADSP-21061 architecture and functionality. For detailed information on the ADSP-21000 Family core architecture and instruction set, refer to the ADSP-21061 SHARC User’s Manual, Revision 2.1. ...
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... WR is not later asserted (e.g conditional write instruction multiprocessing system output by the bus master and is input by all other ADSP-21061s to determine if the multiprocessor memory access is a read or write asserted at the same time as the address output. A host processor using synchronous writes must assert this pin when writing to the ADSP-21061(s) ...
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... DMA transfers and gain access to the external bus. CPA is an open-drain output that is connected to all ADSP-21061s in the system. The CPA pin has an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, the CPA pin should be left unconnected. ...
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... CLKIN I Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified frequency. RESET I/A Processor Reset. Resets the ADSP-21061 to a known state and begins program execution at the program memory location specified by the hardware reset vector address ...
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... ICE connector and the farthest device sharing the EZ-ICE JTAG pin should be limited to 15 inches maximum for guaranteed operation. This length restriction must include EZ-ICE JTAG signals that are routed to one or more ADSP-2106x devices combination of ADSP-2106x devices and other JTAG devices on the chain. ...
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... ADSP-21061/ADSP-21061L OTHER JTAG CONTROLLER Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems TDI EMU TCK TMS TRST TDO CLKIN ADSP-2106x #1 TDI TDO TDI TDI EZ-ICE JTAG CONNECTOR TCK TMS EMU TRST TDO CLKIN OPTIONAL TDI TDO TDI TDO 5k * TDI TDO ...
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... Max Max 1 25° 2 HBG, REDY, DMAG1, DMAG2, BMS, BR 3–0 = 001 and another ADSP-21061 is not requesting bus 2–0 = 001 and another ADSP-21061L 2–0 Unit V ° RPBA, CPA, TFS0, 2–0 Max Unit V 0 μA 10 μA 150 μA 10 μA 10 μA 350 μA 1 ...
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... DDINLOW 4 Idle denotes ADSP-21061L state during execution of IDLE instruction. 5 Idle16 denotes ADSP-2106x state during execution of IDLE16 instruction. a complete discussion of the code used to measure power dissi- pation, see the technical note “SHARC Power Dissipation DD Measurements.” ...
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... EXT cannot INT Rev Page July 2007 ADSP-21061/ADSP-21061L ), but selects can switch on each cycle. CK with the following assumptions: EXT (32-bit 1/(4t ), with 50% of the pins switching CK CK equation is calculated for each class of pins that can EXT × ...
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... Max Max Max 1 25° 2 HBG, REDY, DMAG1, DMAG2, BMS, BR 3–0 = 001 and another ADSP-21061 is not requesting bus 2–0 = 001 and another ADSP-21061L 2–0 Unit V ° RPBA, CPA, TFS0, 2–0 Max Unit V 0 μA 10 μA 150 μA 10 μA 10 μA 350 μ ...
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... IDDINLOW 4 Idle denotes ADSP-21061L state during execution of IDLE instruction. 5 Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction. a complete discussion of the code used to measure power dissi- pation, see the technical note “SHARC Power Dissipation DD Measurements.” ...
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... ADSP-21061/ADSP-21061L EXTERNAL POWER DISSIPATION (3.3 V) Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: × ...
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... ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. PACKAGE MARKING INFORMATION The information presented in Figure 8 the package branding for the ADSP-21061 processor. For a complete listing of product availability, see Page 53. a ADSP-21061 tppZccc vvvvvv ...
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... DD 2 Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu- nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset. CLKIN ...
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... IRQ2–0 Timer Table 10. Timer Parameter Switching Characteristic t CLKIN High to TIMEXP DTEX CLKIN t DTEX TIMEXP SIR t HIR t IPW Figure 11. Interrupts Figure 12. Timer Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max 18 + 3DT 3DT/4 2 and 3.3 V Min Max 15 t DTEX Unit Unit ns ...
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... ADSP-21061/ADSP-21061L Flags Table 11. Flags Parameter Timing Requirements t FLAG3–0 IN Setup Before CLKIN High SFI t FLAG3–0 IN Hold After CLKIN High HFI t FLAG3–0 IN Delay After RD/WR Low DWRFI t FLAG3–0 IN Hold After RD/WR Deasserted HFIWR Switching Characteristics t FLAG3–0 OUT Delay After CLKIN High ...
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... Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21061 is the Table 12. Memory Read—Bus Master Parameter Timing Requirements t Address, Selects Delay to Data Valid DAD t RD Low to Data Valid ...
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... ADSP-21061/ADSP-21061L Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21061 is the Table 13. Memory Write—Bus Master Parameter Timing Requirements t ACK Delay from Address, Selects DAAK 1 t ACK Delay from WR Low ...
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... ADRCLK Delay After CLKIN DADCCK t ADRCLK Period ADRCK t ADRCLK Width High ADRCKH t ADRCLK Width Low ADRCKL 1 This specification applies to the ADSP-21061KS-200 ( MHz) operating The falling edge of MSx, SW, BMS is referenced. 3 ACK delay/setup: User must meet DAAK DSAK (high). 4 See Example System Hold Time Calculation on Page 44 Bus Master on Page these switching characteristics must meet the slave’ ...
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... ADSP-21061/ADSP-21061L CLKIN t DADCCK ADDRCLK t DADRO ADDRESS, BMS, SW, MSx PAGE ACK (IN) READ CYCLE RD DATA (IN) WRITE CYCLE WR DATA (OUT) t ADRCK t t ADRCKH ADRCKL t DAAK t DPGC t t DRWL t DRWL t SDDATO Figure 16. Synchronous Read/Write—Bus Master Rev Page July 2007 t HADRO t HACK SACKC t DRDO t t HSDATI ...
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... WAIT register) is disabled; when MMSWS is enabled, t SRWLI 2 This specification applies to the ADSP-21061LKS-176 (3 MHz) and the ADSP-21061KS-200 ( MHz), operating at t preceding timing specification of the same name. 3 See Example System Hold Time Calculation on Page 44 ...
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... ADSP-21061/ADSP-21061L CLKIN ADDRESS, SW ACK READ ACCESS RD DATA (OU T) WRITE ACCESS W R DATA (IN WLI Figure 17. Synchronous Read/Write—Bus Slave Rev Page July 2007 ATW ...
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... For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21061” section in the ADSP-21061 SHARC User’s Manual, Revision 2.1. ...
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... ADSP-21061/ADSP-21061L CLKIN t SHBRI HBR HBG(OUT) BRx (OUT) CPA (OUT, O/D) HBG (IN) BRx, CPA (IN, O/D) RPBA HBR CS t DRDYCS REDY (O/D) REDY (A/D) HBG(OUT O/D = OPEN-DRAIN, A/D = ACTIVEDRIVE t HHBRI t DHBGO t HHBGO t DBRO t HBRO t DCPAO t SRPBAI t HRPBAI t TRDYHG t HBGRCSV Figure 18. Multiprocessor Bus Request and Host Bus Request Rev ...
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... RDYPWR t REDY (O/D) or (A/D) Disable to CLKIN SRDYCK 1 This specification applies to the ADSP-21061KS-200 ( MHz) operating For the ADSP-21061L (3.3 V), this specification is 13.5 ns max. can drive the RD and WR pins to access the ADSP-21061’s internal memory or IOP registers. HBR and HBG are assumed low for this timing. ...
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... REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/ OPEN-DRAIN, A/D = ACT IVE DRIVE O/D = OPEN-DRAIN, A/D = ACTIVE DRIVE Figure 19. Synchronous REDY Timing DATR YPR ATWH Figure 20. Asynchronous Read/Write—Host to ADSP-21061 Rev Page July 2007 t SRDYCK RWH TWH ...
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... STSCK MIENA, MIENS, MIENHG t DATEN t ACKEN t ADCEN Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max DT/2 –1 – DT/8 –1.5 – DT/8 –1.5 – DT/8 0 – DT/4 1.5 – DT/4 2.0 – DT 5DT/16 0 – DT/8 7 – DT/8 7.5 + DT/4 – ...
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... ADSP-21061/ADSP-21061L HBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE) Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion) t MENHBG Rev Page July 2007 t MTRHBG ...
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... SDATDGL be driven t after DMARx is brought high. DATDRH 3 For the ADSP-21061L (3.3 V), this specification is 23.5 + 7DT/8 ns min valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH the number of extra cycles that the access is prolonged. ...
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... SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DEVICE) DATA (FROM EXTERNAL DEVICE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ADDR MSx, SW *MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER TIMING SPECIFICATIONS FOR ADDR31– ...
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... Transmit Data Delay After TCLK DDTE t Transmit Data Hold After TCLK HODTE 1 Referenced to drive edge RFS Setup Before RCLK Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max 3 and 3.3 V Min Max and 3.3 V Min Max and 3.3 V ...
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... TCLK/RCLK Delay from CLKIN DCLK t SPORT Disable After CLKIN DPTR 1 Referenced to drive edge. 2 For the ADSP-21061L (3.3 V), this specification is 3.5 ns min. Table 27. Serial Ports—External Late Frame Sync Parameter Switching Characteristics t Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0 DDTLFSE t ...
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... SPORT ENABLE AND THREE-STATE LATENCY TFS (EXT) IS TWO CYCLES NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING. Figure 24. Serial Ports Rev Page July 2007 ADSP-21061/ADSP-21061L SAMPLE EDGE t SCLKW t DFSE t t HFSE ...
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... ADSP-21061/ADSP-21061L RCLK RFS DT TCLK TFS DT EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE HDTE/I DDTENFS 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I TDDTENFS t HDTE/I 1ST BIT t DDTLFSE Figure 25. Serial Ports—External Late Frame Sync Rev ...
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... TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS. TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS Table 28 and TCK t t STAP HTAP t DTDO t DSYS Figure 26. JTAG Test Access Port and Emulation Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max 18 SSYS HSYS Unit ...
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... Figure 29. Voltage Reference Levels for AC Measurements (Except Output Output Drive Characteristics 27). If multiple Figure 30 output drivers of the ADSP-21061 (5 V) and ADSP-21061L (3 V). The curves represent the current drive capability and switching behavior of the output drivers as a function of resistive and capacitive loading. ...
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... Figure 32. Typical Output Rise Time (0 2.0 V) vs. Load Capacitance 3.75 4.50 5. NOMINAL 140 160 180 200 Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Maximum ) vs. Load Capacitance DD Rev Page July 2007 ADSP-21061/ADSP-21061L RISE TIME Y = 0.009x + 1.1 FALL TIME Y = 0.005x + 0 100 120 140 160 ...
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... ADSP-21061/ADSP-21061L Input/Output Characteristics (3.3 V) 120 100 3.3V, +25° 3.0V, +85° 3.0V, +85° 3.3V, +25° 100 OL - 120 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 34. Typical Drive Currents ( 0.0796x + 1. RISE TIME FALL TIME 100 120 LOAD CAPACITANCE (pF) Figure 35. Typical Output Rise Time (10 ...
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... The slug is flush with the top surface of the package. Note that the metal slug is internally connected to GND through the device substrate. The ADSP-21061L is available in 240-lead MQFP and 225-ball plastic BGA packages. All packages are specified for a case temperature (T ensure that the T ...
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... ADSP-21061/ADSP-21061L 225-BALL PBGA PIN CONFIGURATIONS Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments Pin PBGA Pin Name Pin Number Name BMS A01 ADDR25 ADDR30 A02 ADDR26 DMAR2 A03 MS2 DT1 A04 ADDR29 RCLK1 A05 DMAR1 TCLK0 A06 TFS1 RCLK0 A07 CPA ...
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... Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments (Continued) Pin PBGA Pin PBGA Name Pin Number Name Pin Number DATA41 C13 DATA26 F13 DATA38 C14 DATA28 F14 DATA36 C15 DATA27 F15 DATA42 DATA44 DATA47 BR3 BR2 DATA39 DATA43 DATA45 DATA36 DATA38 ...
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... ADSP-21061/ADSP-21061L 240-LEAD MQFP PIN CONFIGURATIONS Table 33. ADSP-21061 MQFP/ED (SP-240); ADSP-21061L MQFP (S-240) Pin Assignments Pin Name Pin No. Pin Name Pin No. TDI 1 ADDR20 41 TRST 2 ADDR21 GND 43 DD TDO 4 ADDR22 44 TIMEXP 5 ADDR23 45 EMU 6 ADDR24 46 ICSA FLAG3 8 GND 48 FLAG2 FLAG1 10 ADDR25 50 FLAG0 11 ADDR26 51 GND ...
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... Figure 39. 240-Lead Metric Quad Flat Package, Thermally Enhanced [MQFP/ED] (SP-240-2) 34.60 BSC SQ 29.50 REF 4.10 SQ 3.78 3.55 240 1 PIN 1 HEAT SLUG TOP VIEW (PINS DOWN VIEW A 0.27 MAX 0.50 0.17 MIN BSC LEAD PITCH Rev Page July 2007 ADSP-21061/ADSP-21061L 181 180 24.00 REF SQ 32.00 BSC SQ 121 120 3.92 45° (4 PLACES) ...
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... ADSP-21061/ADSP-21061L 0.75 0.60 0.45 SEATING PLANE 0.50 BSC 0.27 0.17 0.08 MAX COPLANARITY 0.50 0.25 2.70 MAX 34.85 34.60 SQ 34.35 4.10 32.00 BSC SQ MAX PIN 3.50 3.40 3.20 Figure 40. 240-Lead Metric Quad Flat Package, [MQFP] (S-240) 23.20 23.00 SQ 22.80 BALL A1 INDICATOR 18 ...
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... Requirements for Surface-Mount Design and Land Pattern Standard. Table 34. BGA Data for Use with Surface-Mount Design Package 225-Ball Grid Array (PBGA) ORDERING GUIDE Temperature Model Range ADSP-21061KS-133 0°C to 85°C 1 ADSP-21061KSZ-133 0°C to 85°C ADSP-21061KS-160 0°C to 85°C 1 ADSP-21061KSZ-160 0°C to 85°C ADSP-21061KS-200 0° ...
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... ADSP-21061/ADSP-21061L Rev Page July 2007 ...
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... Rev Page July 2007 ADSP-21061/ADSP-21061L ...
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... ADSP-21061/ADSP-21061L ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00170-0-7/07(C) Rev Page July 2007 ...