ADSP-2188MBCA-266 Analog Devices Inc, ADSP-2188MBCA-266 Datasheet

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... DATA ADDRESS GENERATORS DAG1 DAG2 ARITHMETIC UNITS ALU MAC ADSP-2100 BASE ARCHITECTURE ICE-Port is a trademark of Analog Devices, Inc. FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL MEMORY PROGRAM DATA PROGRAM MEMORY MEMORY SEQUENCER 48K 24 BIT 56K 16 BIT PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA ...

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... Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory Mapped Registers (New to the ADSP-2188M I/O Space (Full Memory Mode Composite Memory Select (CMS Byte Memory Select (BMS Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte Memory DMA (BDMA, Full Memory Mode Internal Memory DMA Port (IDMA Port ...

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... PC monitor software plus assembler, linker, simulator, and PROM splitter software. The ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • ...

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... Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permit- ting the ADSP-2188M to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2188M can fetch an operand from program memory and the next instruction in the same cycle ...

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... The ADSP-2188M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2188M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section ...

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... ADSP-2188M Common-Mode Pins Pin Name # of Pins RESET BGH 1 DMS 1 PMS 1 IOMS 1 BMS 1 CMS IRQ2 1 PF7 IRQL1 1 PF6 IRQL0 1 PF5 IRQE 1 PF4 Mode D 1 PF3 Mode C 1 PF2 Mode B 1 PF1 Mode A 1 PF0 CLKIN, XTAL 2 CLKOUT 1 SPORT0 5 SPORT1 5 IRQ1:0, FI, FO PWD ...

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... Memory Interface Pins The ADSP-2188M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter- nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. ...

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... ADSP-2188M Terminating Unused Pins The following table shows the recommendations for terminating unused pins. Pin Terminations I/O 3-State Reset Pin Name (Z) State XTAL I I CLKOUT O O A13 (Z) Hi-Z IAD 12:0 I/O (Z) Hi (Z) Hi-Z D23:8 I/O (Z) Hi I/O (Z) Hi-Z IWR I/O (Z) Hi-Z ...

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... In Idle mode IDMA, BDMA and autobuffer cycle steals still occur. Slow Idle The IDLE instruction is enhanced on the ADSP-2188M to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a program- mable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction ...

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... The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled inter- rupt is received, the ADSP-2188M will remain in the idle state for maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. ...

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... RESET The RESET signal initiates a master reset of the ADSP-2188M. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time ...

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... External Overlay 2 Program Memory Program Memory (Full Memory Mode 24-bit-wide space for storing both instruction opcodes and data. The ADSP- 2188M has 48K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory over- lay spaces using the external data bus. ...

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... Data Memory (Full Memory Mode 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2188M has 56K words on Data Memory RAM on-chip. Part of this space is used by 32 memory- mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus ...

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... BDMA feature. The byte memory space con- sists of 256 pages, each of which is 16K × 8. The byte memory space on the ADSP-2188M supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows meg × ...

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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2188M. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...

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... Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and • Halting program execution Mode is enabled, the ADSP-2188M will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2188M is performing an external memory access ...

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... The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take con- trol of the ADSP-2185M in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. ...

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... DSP components statisti- cally vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-2188M (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your target system must have 10 kΩ pull-up resistors connected when the EZ-ICE is being used ...

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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7 BR. 9 Idle refers to ADSP-2188M state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 12, 13, 14), 30% are Type 2 DD and Type 6, and 20% are idle instructions ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2188M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... Total power dissipation for this example is P 2°C/W 7.4°C/W Output Drive Currents Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2188M. The curves represent the current drive capability of the output drivers as a function of output voltage. ) is: –20 –40 –60 – ...

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... MULTIFUNCTION (TYPES 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4 IDLE REFERS TO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND Capacitive Loading Figure 16 and Figure 17 show the capacitive loading character- 145mW istics of the ADSP-2188M. 129mW 30 111mW ...

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... If multiple pins (such as the data bus) are enabled, the mea- surement value is that of the first pin to start driving. REFERENCE SIGNAL V OH (MEASURED) OUTPUT V OL (MEASURED) 1.5V 2.0V 1.5V 0.8V OUTPUT ADSP-2188M ) is the interval from when a refer- ENA t MEASURED t ENA t V DIS (MEASURED) V (MEASURED) – 0.5V 2.0V OH 1.0V V (MEASURED) +0 ...

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... ADSP-2188M Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High CKOH Control Signals Timing Requirements: RESET Width Low ...

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... IFS IFH the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. ...

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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. ...

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... PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, IOMS, CMS RD D0–D23 WR Min 0 0.5t – 0.25t – 0.25t – 0.25t – 0.5t – RDA t ASR RWR CRD t t RDD RDH t AA ADSP-2188M Max Unit 0.5t – 0.75t – 0.25t + ...

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... ADSP-2188M Parameter Memory Write Switching Characteristics: Data Setup before WR High t DW Data Hold after WR High Pulsewidth Low to Data Enabled t WDE A0–A13, xMS Setup before WR Low t ASW Data Disable before Low t DDR CLKOUT High to WR Low t CWR A0–A13, xMS, Setup before WR Deasserted ...

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... FRAME MODE RFS OUT MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) TFS IN ALTERNATE FRAME MODE RFS IN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) Min 26 0.25t SCP t t SCS SCH SCDD t SCDV t t SCDH SCDE t TDE t TDV t RDV t TDE t TDV t RDV ADSP-2188M Max Unit 0.25t + SCK t SCP ...

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... ADSP-2188M Parameter IDMA Address Latch Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup before Address Latch End IASU t IAD15–0 Address Hold after Address Latch End IAH IACK Low before Start of Address Latch t IKA t Start of Write or Read after Address Latch End ...

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... End of Write = IS High or IWR High Write Pulse ends before IACK Low, use specifications t If Write Pulse ends after IACK Low, use specifications t 4 IACK IS IWR IAD15–0 Min IDSU IDH , t . IKSU IKH t IKW t IKHW t IWP t IDH t IDSU DATA ADSP-2188M Max Unit ...

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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. IACK IS IWR IAD15– ...

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... End of Read = IS High or IRD High read or first half of PM read. 4 Second half of PM read. IACK IS IRD IAD15–0 Min 0. IKHR t IKR t IRK t t IKDS IRDE PREVIOUS READ DATA DATA t IRDV t t IRDH1 or IRDH2 ADSP-2188M Max 10 – – – IKDH t IKDD Unit ...

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... ADSP-2188M Parameter 1, 2 IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read (DM/PM1) IRP1 t Duration of Read (PM2) IRP2 Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Hold after End of Read IKDH t IAD15–0 Data Disabled after End of Read ...

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... Disabled by default. Start of Read = IS Low and IRD Low. Previous data remains until end of read End of Read = IS High or IRD High IACK t IKR t IKHR IS t IRP IRD t IRDE PREVIOUS IAD15–0 DATA t IRDV ADSP-2188M Min Max IKDH t IKDD Unit ...

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... A10/IAD9 9 A11/IAD10 A12/IAD11 10 11 A13/IAD12 12 GND 13 CLKIN XTAL DDEXT 16 CLKOUT GND DDINT BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 100-LEAD LQFP PIN CONFIGURATION ADSP-2188M TOP VIEW (Not to Scale) 75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 DDEXT 66 GND D7/IWR 63 D6/IRD 62 D5/IAL 61 D4/IS 60 GND INT ...

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... D8 GND 66 GND SCLK1 67 V ERESET 68 D9 RESET 69 D10 EMS 70 D11 EE 71 GND ECLK 72 D12 ELOUT 73 D13 ELIN 74 D14 EINT 75 D15 ADSP-2188M Pin No. Pin Name 76 D16 77 D17 78 D18 79 D19 80 GND 81 D20 82 D21 83 D22 84 D23 DDINT 85 FL2 86 FL1 87 FL0 88 PF3 [MODE D] 89 ...

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... ADSP-2188M 144-Ball Mini-BGA Package Pinout (Bottom View GND GND D22 NC D16 D17 D18 D20 D14 NC D15 D19 GND NC D12 D13 D10 GND V GND DDEXT D11 NC NC D5/IAL D4/IS GND NC GND D3/IACK D1/IAD14 DDINT DDINT EBG BR EBR ERESET EINT ELOUT ELIN RESET ...

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... H12 A13/IAD12 J01 NC J02 A12/IAD11 J03 A11/IAD10 J04 FL1 J05 NC J06 NC J07 D7/IWR J08 D11 J09 D8 J10 NC J11 D9 J12 ADSP-2188M Pin Name Ball # Pin Name XTAL K01 NC NC K02 NC GND K03 NC BMS A10/IAD9 K04 DMS NC K05 NC K06 RFS0 NC K07 TFS1/IRQ1 D6/IRD ...

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... ADSP-2188MBST-266 –40°C to +85°C ADSP-2188MKCA-300 0°C to 70°C ADSP-2188MBCA-266 –40°C to +85°C In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labeled TQFP packages (1.6 mm thick) are now designated as LQFP. OUTLINE DIMENSIONS Dimensions shown in millimeters ...