ADSP-2187LKSTZ-210 Analog Devices Inc, ADSP-2187LKSTZ-210 Datasheet

IC DSP CONTRLR 16BIT 100-TQFP

ADSP-2187LKSTZ-210

Manufacturer Part Number
ADSP-2187LKSTZ-210
Description
IC DSP CONTRLR 16BIT 100-TQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2187LKSTZ-210

Interface
Host Interface, Serial Port
Clock Rate
52MHz
Non-volatile Memory
External
On-chip Ram
160kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Device Core Size
16b
Format
Fixed Point
Clock Freq (max)
52.5MHz
Mips
52.5
Device Input Clock Speed
52.5MHz
Ram Size
160KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP-2187LKSTZ210
PERFORMANCE FEATURES
Up to 19 ns instruction cycle time, 52 MIPS sustained
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
Low power dissipation in idle mode
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
Up to 160K bytes of on-chip RAM, configured
Dual-purpose program memory for both instruction and
Independent ALU, multiplier/accumulator, and barrel shifter
2 independent data address generators
Powerful program sequencer provides zero overhead loop-
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
ICE-Port is a trademark of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
performance
instruction cycle
pation with 400 CLKIN cycle recovery from power-down
condition
syntax), with instruction set extensions
Up to 32K words program memory RAM
Up to 32K words data memory RAM
data storage
computational units
ing conditional instruction execution
DATA ADDRESS
GENERATORS
DAG1
ALU
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG2
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
MAC
SEQUENCER
PROGRAM
SHIFTER
PROGRAM MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY ADDRESS
Figure 1. Functional Block Diagram
DATA MEMORY DATA
32K
PROGRAM
MEMORY
UP TO
24-BIT
SPORT0
POWER-DOWN
SERIAL PORTS
MEMORY
CONTROL
32K
SPORT1
MEMORY
UP TO
DATA
16-BIT
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SYSTEM INTERFACE FEATURES
16-bit internal DMA port for high-speed access to on-chip
4M-byte memory interface for storage of data tables and pro-
8-bit DMA to byte memory for transparent program and data
Programmable memory strobe and separate I/O memory
Programmable wait state generation
2 double-buffered serial ports with companding hardware
Automatic booting of on-chip program memory from byte-
6 external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port emulator interface supports debugging in final
memory (mode selectable)
gram overlays (mode selectable)
memory transfers (mode selectable)
space permits “glueless” system design
and automatic data buffering
wide external memory, for example, EPROM, or through
internal DMA Port
systems
TIMER
PROGRAMMABLE
FLAGS
AND
I/O
©2008 Analog Devices, Inc. All rights reserved.
DSP Microcomputer
FULL MEMORY MODE
CONTROLLER
HOST MODE
EXTERNAL
EXTERNAL
EXTERNAL
BYTE DMA
INTERNAL
ADDRESS
DATA
DATA
PORT
OR
BUS
BUS
BUS
DMA
www.analog.com

Related parts for ADSP-2187LKSTZ-210

ADSP-2187LKSTZ-210 Summary of contents

Page 1

... CLKIN cycle recovery from power-down condition Low power dissipation in idle mode INTEGRATION FEATURES ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions Up to 160K bytes of on-chip RAM, configured Up to 32K words program memory RAM Up to 32K words data memory RAM ...

Page 2

... ESD Sensitivity ................................................... 22 Timing Specifications ........................................... 22 Power Supply Current .......................................... 36 Power Dissipation ............................................... 37 Output Drive Currents ......................................... 40 Power-Down Current ........................................... 41 Capacitive Loading – ADSP-2184L, ADSP-2186L ........ 42 Capacitive Loading – ADSP-2185L, ADSP-2187L ........ 42 Test Conditions .................................................. 43 Environmental Conditions .................................... 43 LQFP Package Pinout ........................................... 44 BGA Package Pinout ............................................ 45 Outline Dimensions ................................................ 46 Surface Mount Design .......................................... 47 Ordering Guide ..................................................... 47 ...

Page 3

... LQFP and 144-ball BGA packages. Fabricated using high-speed, low-power, CMOS processes, ADSP-218xL series members operate with instruction cycle time (ADSP-2185L and ADSP-2187L instruc- tion cycle time (ADSP-2184L and ADSP-2186L). Every instruction can execute in a single processor cycle. The ADSP-218xL’s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel ...

Page 4

... ADSP-218xL series members incorporate two complete syn- chronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Following is a brief list of the capabilities of the ADSP-218xL SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • ...

Page 5

... Mode D applies to the ADSP-2187L processor only. 2 Considered as standard operating settings. Using these configurations allows for easier design and better memory management. during power-down, reconfigure PF2 input, as the pull pull-down resistance will hold the pin in a known state, and will not switch. ...

Page 6

... Power-down acknowledge pin (PWDACK) indicates when the processor has entered power-down. Idle When the ADSP-218xL is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE instruc- tion ...

Page 7

... D23–0 MEMORY DATA TWO 8K PMS PM SEGMEN TS DMS TWO 8K CMS DM SEGMEN BGH PWD NOTE: MODE D APPLIES TO THE ADSP-2187L P ROCES SOR ON LY Figure 2. Basic System Interface Rev Page January 2008 Figure 3. Capacitor values are HOST MEMORY MODE ADSP-218xL CLK IN 1/2 CLOCK OR XTAL CRYSTAL 1 A0 FL0– ...

Page 8

... Data Memory (Full Memory Mode 16-bit-wide space used for the storage of data variables and for memory-mapped con- trol registers. The ADSP-218xL series has up to 32K words of Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus ...

Page 9

... Figure 6. ADSP-2186 Memory Architecture PROGRAM MEMORY MODEB = 1 0x3FFF 0x3FFF RESERVED 0x2000 0x2000 0x1FFF 0x1FFF EXTERNAL PM 0x0000 0x0000 Figure 7. ADSP-2187 Memory Architecture Rev Page January 2008 PROGRAM MEMORY DATA MEMORY MODEB = 0 0x3FFF 32 MEMORY-MAPPED CONTROL REGISTERS PM OVERLAY 1,2 0x3FE0 (EXTERNAL PM) 0x3FDF PM OVERLAY 0 INTERNAL DM ...

Page 10

... Two instructions were added to the core ADSP-2100 family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0– ...

Page 11

... BDMA feature. The byte memory space consists of 256 pages, each of which is 16K The byte memory space on the ADSP-218xL series supports read and write operations as well as four different data formats. The byte memory uses data bits 15–8 for data. The byte mem- ory uses data bits 23– ...

Page 12

... DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-218xL to write the address onto the IAD14–0 bus into the IDMA Control Register 15 is set to 0, IDMA latches the address. If Bit 15 is set to 1, IDMA latches into the OVLAY register ...

Page 13

... IDMA Port Booting ADSP-218xL series members can also boot programs through its internal DMA port. If Mode Mode and Mode the ADSP-218xL boots from the IDMA port. IDMA feature ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L can load as much on-chip memory as desired. Program execu- tion is held off until the host writes to on-chip program memory location 0 ...

Page 14

... Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. • The syntax is a superset ADSP-2100 Family assembly lan- guage and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-218xL’ ...

Page 15

... The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-218xL in the target system. This causes the proces- sor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in the system ...

Page 16

... EZ-ICE board’s DSP. ADDITIONAL INFORMATION This data sheet provides a general overview of ADSP-218xL series functionality. For additional information on the architec- ture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference and the ADSP-218x DSP Instruction Set Reference. Rev Page January 2008 ...

Page 17

... PIN DESCRIPTIONS ADSP-218xL series members are available in a 100-lead LQFP package and a 144-ball BGA package. In order to maintain max- imum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are Table 9 ...

Page 18

... SPORT configuration determined by the DSP System Control Register. Software configurable. MEMORY INTERFACE PINS ADSP-218xL series members can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...

Page 19

... O ( (Z) BGH O IRQ2/PF7 I/O (Z) IRQL1/PF6 I/O (Z) IRQL0/PF5 I/O (Z) IRQE/PF4 I/O (Z) PWD I SCLK0 I/O RFS0 I/O DR0 I TFS0 I/O DT0 O ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Reset 2 3 State High-Z Caused High-Z BR, EBR High-Z IS High-Z BR, EBR High-Z BR, EBR High-Z BR, EBR I High-Z BR, EBR I BR, EBR High-Z I High-Z BR, EBR ...

Page 20

... ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 12. Unused Pin Terminations (Continued) I/O 1 Pin Name 3-State (Z) SCLK1 I/O RFS1/IRQ0 I/O DR1/FI I TFS1/IRQ1 I/O DT1/ EBR I EBG O ERESET I EMS O EINT I ECLK I ELIN I ELOUT O 1 CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used. ...

Page 21

... Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–FL0, BGH. 5 Although specified for TTL outputs, all ADSP-218xL outputs are CMOS-compatible and will drive Guaranteed but not tested. 7 Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0. ...

Page 22

... A13–1, PF7–0) and input only pins (CLKIN, RESET, BR, DR0, DR1, PWD). 2 Applies to output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH). PACKAGE INFORMATION The information presented in Figure 15 the package branding for the ADSP-218xL processors. For a complete listing of product availability, see Page 47. a ADSP-218xL tppZ-cc vvvvvv ...

Page 23

... CLKOUT MODE A D RESET ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L ADSP-2184L, ADSP-2186L Min Max 50 150 20 20 0.5t – 0.5t – CKI t CKIH t CKIL t CKOH t CKH t CKL RSP Figure 16. Clock Signals and Reset Rev Page January 2008 ADSP-2185L, ADSP-2187L Min Max Unit 38 100 0.5t – 0.5t – ...

Page 24

... IFS IFH following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. ...

Page 25

... BGH High to xMS, RD, WR Enable SEH asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2 xMS = PMS, DMS, CMS, IOMS, BMS. 3 For the ADSP-2187L, this specification is 0 ...

Page 26

... RD High Low RWR w = wait states × xMS = PMS, DMS, CMS, IOMS, BMS. 3 For the ADSP-2187L, this specification min. CLKOUT ADDRESS LINES 1 DMS, PMS, BMS, IOMS, CMS RD DATA LINES ADDRESS LINES FOR ACCESSES ARE: BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs) I/O SPACE: A10– ...

Page 27

... CK 2 xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT ADDRESS LINES 1 DMS, PMS, BMS, CMS, IOMS WR DATA LINES ADDRESS LINES FOR ACCESSES ARE: BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs) I/O SPACE: A10–0 EXTERNAL PM AND DM: A13–0 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L ASW CWR WDE 2 DATA LINES FOR ACCESSES ARE: BDMA: D15– ...

Page 28

... TFS (Alt Valid TDV t SCLK High to DT Disable SCDD t RFS (Multichannel, Frame Delay Zero Valid RDV 1 For the ADSP-2187L, this specification min. 2 For the ADSP-2187L, this specification min. 3 For the ADSP-2185L, and the ADSP-2187L, this specification min. Min 0.25t Rev Page January 2008 ...

Page 29

... ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L CLKOUT SCLK TFS IN RFS RFS O UT TFS TFS LTER FRA RFS LTIC ODE , MFD = TFS IN ALTE RFS IN MU LTIC ODE , MFD = 0 ) Figure 21. Serial Ports Rev Page January 2008 ...

Page 30

... Address Latch Start After Address Latch End IALD 1 Start of Address Latch = IS Low and IAL High. 2 End of Address Latch = IS High or IAL Low. 3 For the ADSP-2187L, this specification min. 4 Start of Write or Read = IS Low and IWR Low or IRD Low. IACK IAL IS IAD15–0 IRD OR IWR ...

Page 31

... Start of Write = IS Low and IWR Low. 2 End of Write = IS High or IWR High Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 5 For the ADSP-2185L, and the ADSP-2187L, this specification min., and 15 ns max. IACK IS IWR IAD15–0 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L ...

Page 32

... If Write Pulse ends after IACK Low, use specifications t 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. 5 For the ADSP-2185L, and the ADSP-2187L, this specification min., and 15 ns max. ...

Page 33

... IAD15–0 Previous Data Hold After Start of Read (PM2) IRDH2 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. 3 For the ADSP-2185L, and the ADSP-2187L, this specification min., and 15 ns max. 4 For the ADSP-2187L, this specification max read or first half of PM read. 6 Second half of PM read. ...

Page 34

... Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies. 3 Start of Read = IS Low and IRD Low Read or first half of PM Read. 5 For the ADSP-2186L, this specification also has a max value Second half of PM Read. 7 For the ADSP-2186L, this specification also has a max value End of Read = IS High or IRD High – 5. ...

Page 35

... IAD15–0 Previous Data Valid After Start of Read IRDV 1 Applies to the ADSP-2187L only. 2 Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register external host writing to the register. Disabled by default. ...

Page 36

... Supply Current (Dynamic Specifications subject to change without notice. 2 Idle refers to ADSP-218xL state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 12, 13, 14), 30% are Type 2 and DD Type 6, and 20% are idle instructions ...

Page 37

... CLKOUT 1 1 Total power dissipation for this example 50.7 mW. INT ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • External data memory writes occur every other cycle with 50% of the data pins switching. • Each address and data pin has total load at the pin. ...

Page 38

... W 90 84m – MHz C K POWER, IDLE 25m 20m 16m – MHz C K POWER, IDLE n MODES 20mW 20 13mW 15 10m W 10 12mW 9mW – MHz Figure 29. Power vs. Frequency (ADSP-2185L) 19 7mW 161m W 13 0mW 5mW 28m W 22m 28mW IDLE(16) IDLE(128 ND ...

Page 39

... EXECUTING FROM INTERNAL MEMORY. 50% Of the INSTRUCTIONS ARE MULTIFUNCTION (TYPES 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4. IDLE REFERSTO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V Figure 30. Power vs. Frequency (ADSP-2186L) ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L 230 210 169mW ...

Page 40

... ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L OUTPUT DRIVE CURRENTS Figure 32 through Figure 35 show typical I-V characteristics for the output drivers on the ADSP-218xL processors. The curves represent the current drive capability of the output drivers as a function of output voltage 3.3V @ +25 C DDEXT V DDEXT 3.0V @ +85 C DDEXT 3.0V @ +85 C DDEXT – ...

Page 41

... Figure 39 show the typical power-down supply current. Note that these graphs reflect ADSP-218xL operation in lowest power mode. (See the “System Interface” chapter of the ADSP-218x DSP Hardware Reference for details). Current reflects device operating with no input loads. 10000 1000 100 ...

Page 42

... C – Figure 41. Typical Output Valid Delay or Hold vs. Load Capacitance, C (at Maximum Ambient Operating Temperature) CAPACITIVE LOADING – ADSP-2185L, ADSP-2187L Figure 42 tics of the ADSP-2185L and ADSP-2187L. 180 200 150 200 250 Figure 43. Typical Output Valid Delay or Hold vs. Load Capacitance Rev Page January 2008 ...

Page 43

... Figure 45. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L REFERENCE (MEASURED) OUTPUT 1.5V and t ...

Page 44

... CMS 50 1 Mode D function available on ADSP-2187L only. of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode 29. Pin names in selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit these pins have serial port func- tionality ...

Page 45

... NC F11 C12 D14 F12 1 Mode D function available on ADSP-2187L only. ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode 30. Pin names in selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit these pins have serial port func- tionality ...

Page 46

... ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L OUTLINE DIMENSIONS 10.10 10.00 SQ BALL A1 PAD CORNER TOP VIEW DETAIL A 1.45 1.40 1.35 0.15 SEATING 0.05 0.08 PLANE MAX LEAD COPLANARITY VIEW A ROTATED 90° CCW THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. ...

Page 47

... ADSP-2186LBCA-160R –40°C to +85°C ADSP-2187LKST-160 0°C to 70°C 2 ADSP-2187LKSTZ-160 0°C to 70°C ADSP-2187LKST-210 0°C to 70°C 2 ADSP-2187LKSTZ-210 0°C to 70°C ADSP-2187LBST-160 –40°C to +85°C 2 ADSP-2187LBSTZ-160 –40°C to +85°C ADSP-2187LBST-210 –40°C to +85°C 2 ADSP-2187LBSTZ-210 –40°C to +85°C 1 Ranges shown represent ambient temperature ...

Page 48

... ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00192-0-1/08(C) Rev Page January 2008 ...

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