EP1K10TC100-3N Altera, EP1K10TC100-3N Datasheet - Page 54

• Manufacturer Part Number: EP1K10TC100-3N
• Description: IC ACEX 1K FPGA 10K 100-TQFP
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K10TC100-3N

• Number Of Logic Elements/cells: 576
• Number Of Labs/clbs: 72
• Total Ram Bits: 12288
• Number Of I /o: 66
• Number Of Gates: 56000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Family Name: ACEX™ 1K
• Number Of Usable Gates: 10000
• Number Of Logic Blocks/elements: 576
• # I/os (max): 66
• Frequency (max): 200MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 576
• Ram Bits: 12288
• Device System Gates: 56000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1828; EP1K10TC100-3N

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 30. EAB Synchronous Timing Waveforms
54
t
t
t
t
t
t
t
t
LUT
CLUT
RLUT
PACKED
EN
CICO
CGEN
CGENR
Table 22. LE Timing Microparameters (Part 1 of 2)
EAB Synchronous Read
EAB Synchronous Write (EAB Output Registers Used)
Data-Out
Data-Out
Symbol
Address
Address
Data-In
CLK
CLK
WE
WE
a0
t
EABDATASU
a0
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
t
EABWESU
din1
a1
Tables 22
parameters.
dout0
a1
t
through
EABDATAH
t
EABDATASU
dout1
Parameter
din2
26
a2
describe the ACEX 1K device internal timing
t
t
EABDATAH
t
EABDATACO
EABWCREG
Note (1)
din1
din3
t
a3
EABWEH
t
a2
EABDATACO
t
EABRCREG
din2
d1
Altera Corporation
din3
a2
Conditions
a3
d2
din2