IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 


Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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May 2003, ver. 3.4
Features...
TM
Table 1. ACEX
1K Device Features
Feature
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Altera Corporation
DS-ACEX-3.4
Programmable Logic Device Family
®
Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
Logic array for general logic functions
High density
10,000 to 100,000 typical gates (see
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
Cost-optimized process
Low cost solution for high-performance communications
applications
System-level features
MultiVolt
TM
I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
Low power consumption
Bidirectional I/O performance (setup time [t
output delay [t
]) up to 250 MHz
CO
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Extended temperature range
EP1K10
EP1K30
10,000
30,000
56,000
119,000
576
1,728
3
6
12,288
24,576
136
171
ACEX 1K
Data Sheet
Table
1)
] and clock-to-
SU
EP1K50
EP1K100
50,000
100,000
199,000
257,000
2,880
4,992
10
12
40,960
49,152
249
333
13
1

EP1K10TC100-3 Summary of contents

  • Page 1

    ... Device Features Feature Typical gates Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins Altera Corporation DS-ACEX-3.4 Programmable Logic Device Family ® Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device – ...

  • Page 2

    ... Individual tri-state output enable control for each pin – Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise – Clamp to V user-selectable on a pin-by-pin basis CCIO – Supports hot-socketing TM options for reduced clock delay, Altera Corporation ...

  • Page 3

    ... Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Software design support and automatic place-and-route provided by Altera development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Flexible package options are available in 100 to 484 pins, including the innovative FineLine BGA ...

  • Page 4

    ... All performance results were obtained with Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Table 4. ACEX 1K Device Performance ...

  • Page 5

    ... ACEX 1K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices, which configure ACEX 1K devices via a serial data stream. Configuration data can also be downloaded from system RAM or via the Altera TM MasterBlaster , ByteBlasterMV an ACEX 1K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data ...

  • Page 6

    ... PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. ...

  • Page 7

    ... Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect consists of a 4-input LUT, a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic— ...

  • Page 8

    ... Embedded Array Block (EAB) IOE IOE IOE IOE IOE EAB EAB IOE IOE IOE IOE IOE Embedded Array IOE IOE IOE IOE IOE Logic Array Logic Array Block (LAB) IOE IOE Local Interconnect IOE IOE IOE Altera Corporation Logic Element (LE) ...

  • Page 9

    ... Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Embedded Array Block The EAB is a flexible block of RAM, with registers on the input and output ports, that is used to implement common gate array megafunctions. Because it is large and flexible, the EAB is suitable for functions such as multipliers, vector scalars, and error correction circuits ...

  • Page 10

    ... EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB local interconnect channels. The EAB can use Altera megafunctions to implement dual-port RAM applications where both ports can read or write, as shown in ACEX 1K EAB can also be used in a single-port mode (see ...

  • Page 11

    ... Dedicated Clocks 2 EAB Local Interconnect (1) Note: (1) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB local interconnect channels. Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Port A Port B address_a[] address_b[] data_a[] data_b[] we_a clkena_a ...

  • Page 12

    ... RAM blocks can be combined to form a 256 32 block, and two 512 8 RAM blocks can be combined to form a 512 16 block. Figure 6. Examples of Combining ACEX 1K EABs 256 16 256 2,048 2. 512 8 Figure 6 shows examples of multiple EAB combination. 256 32 Figure 5 shows the ACEX 1K 2,048 2 1,024 4 512 16 512 8 512 8 Altera Corporation ...

  • Page 13

    ... If necessary, all EABs in a device can be cascaded to form a single RAM block. EABs can be cascaded to form RAM blocks 2,048 words without impacting timing. Altera software automatically combines EABs to meet a designer’s RAM specifications. EABs provide flexible options for driving and controlling clock signals. ...

  • Page 14

    ... EP1K10, EP1K30, and EP1K50 devices have 30 LAB local interconnect channels; EP1K100 devices have 34. 14 Dedicated Inputs & Global Signals Row Interconnect 6 4 Carry-In & Cascade- LE1 4 LE2 4 LE3 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 Carry-Out & Cascade-Out Altera Corporation See Figure 13 for details. Column-to-Row Interconnect Column Interconnect ...

  • Page 15

    ... Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Each LAB provides four control signals with programmable inversion that can be used in all eight LEs. Two of these signals can be used as clocks, the other two can be used for clear/preset control. The LAB clocks can be driven by the dedicated clock input pins, global signals, I/O signals, or internal signals via the LAB local interconnect ...

  • Page 16

    ... Therefore, the use of these chains should be limited to speed-critical portions of a design. 16 Carry-In Cascade-In Carry Cascade Table Chain Chain (LUT) Clear/ Preset Logic Clock Select Carry-Out Cascade-Out Register Bypass Programmable Register PRN D Q ENA CLRN Altera Corporation To FastTrack Interconnect To LAB Local Interconnect ...

  • Page 17

    ... Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Carry Chain The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain ...

  • Page 18

    ... ACEX 1K Programmable Logic Device Family Data Sheet Figure 9. ACEX 1K Carry Chain Operation (n-Bit Full Adder) 18 Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain an LUT bn Carry Chain LUT Carry Chain s1 Register LE1 s2 Register LE2 sn Register LEn Register Carry-Out LEn + 1 Altera Corporation ...

  • Page 19

    ... Figure 10. ACEX 1K Cascade Chain Operation AND Cascade Chain d[3..0] d[7..4] d[(4 n – 1)..(4 n – 4)] Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Cascade Chain With the cascade chain, the ACEX 1K architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel ...

  • Page 20

    ... LE—are directed to different destinations to implement the desired logic function. Three inputs to the LE provide clock, clear, and preset control for the register. The Altera software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers ...

  • Page 21

    ... Up/Down Counter Mode Carry-In data1 (ena) data2 (u/d) data3 (data) data4 (nload) Clearable Counter Mode Carry-In data1 (ena) data2 (nclr) data3 (data) data4 (nload) Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Cascade-In LUT Cascade-Out Cascade-In LUT LUT Carry-Out Cascade-Out Cascade-In 3-Input ...

  • Page 22

    ... A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals without using the LUT resources. 22 Figure 11, the first LUT uses the carry-in signal and two data inputs Altera Corporation ...

  • Page 23

    ... Conversely signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The Altera software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’ ...

  • Page 24

    ... CLRN VCC Asynchronous Load without Clear or Preset (Asynchronous PRN D Q CLRN PRN D CLRN Chip-Wide Reset Figure 12 shows examples Asynchronous Preset & Clear labctrl1 PRN D CLRN labctrl2 Chip-Wide Reset NOT labctrl1 Load) data3 (Data) NOT Chip-Wide Reset Q Altera Corporation Q PRN D Q CLRN ...

  • Page 25

    ... Asynchronous Load with Preset When implementing an asynchronous load in conjunction with preset, the Altera software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 presets the register, while asserting LABCTRL1 loads the register. The Altera software inverts the signal that drives DATA3 to account for the inversion of the register’ ...

  • Page 26

    ... LABs. For example one LAB can drive the row and column channels normally driven by a particular LE in the adjacent LAB in the same row, and vice versa. This flexibility enables routing resources to be used more efficiently. 26 Figure 13 shows the ACEX 1K LAB. Altera Corporation ...

  • Page 27

    ... Figure 13. ACEX 1K LAB Connections to Row & Column Interconnect Row Channels Each LE can drive two row channels Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet At each intersection, six row channels can drive column channels. Each LE can switch interconnect access with the adjacent LAB ...

  • Page 28

    ... LAB row B, column 3. 28 summarizes the FastTrack Interconnect routing structure Table 6. ACEX 1K FastTrack Interconnect Resources Device Rows EP1K10 3 EP1K30 6 EP1K50 10 EP1K100 12 shows the interconnection of adjacent LABs and EABs, with Channels per Columns Row 144 24 216 36 216 36 312 52 Altera Corporation Channels per Column ...

  • Page 29

    ... Figure 14. ACEX 1K Interconnect Resources I/O Element (IOE) IOE IOE Row LAB Interconnect A1 Column Interconnect IOE IOE LAB B1 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet IOE IOE IOE IOE LAB A2 LAB B2 IOE IOE IOE IOE I/O Element An IOE contains a bidirectional I/O buffer and a register that can be used ...

  • Page 30

    ... Chip-Wide VCC OE[7..0] Programmable Delay VCC CLK[1..0] CLK[3..2] VCC ENA[5..0] VCC CLRN[1..0] Chip-Wide VCC Chip-Wide OE Register D Q ENA CLRN Reset Chip-Wide Output Enable Output Register D Q ENA Open-Drain CLRN Output Slew-Rate Control Reset Input Register D Q ENA CLRN Reset Altera Corporation ...

  • Page 31

    ... Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet On all ACEX 1K devices, the input path from the I/O pad to the FastTrack Interconnect has a programmable delay element that can be used to guarantee a zero hold time. Depending on the placement of the IOE relative to what it is driving, the designer may choose to turn on the programmable delay to ensure a zero hold time or turn it off to minimize setup time ...

  • Page 32

    ... The chip-wide output enable pin is an active-high pin that can be used to tri-state all pins on the device. This option can be set in the Altera software. The built-in I/O pin pull-up resistors (which are active during configuration) are active when the chip-wide output enable pin is asserted ...

  • Page 33

    ... Interconnect n Note: (1) The values for m and n are shown in Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Row-to-IOE Connections When an IOE is used as an input signal, it can drive two separate row channels. The signal is accessible by all LEs within that row. When an IOE is used as an output, the signal is driven by a multiplexer that selects a signal from the row channels ...

  • Page 34

    ... The values for m and n are shown in lists the ACEX 1K column-to-IOE interconnect resources. Table 9. ACEX 1K Column-to-IOE Interconnect Resources Device Channels per Column (n) Column Channels per Pin (m) EP1K10 EP1K30 EP1K50 EP1K100 Note (1) Each IOE is driven by a m-to-1 multiplexer IOE1 m IOE1 m Table Altera Corporation ...

  • Page 35

    ... The Altera software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software generates pin-outs describing how to lay out a board that takes advantage of this migration. SameFrame pin-out. Figure 18. SameFrame Pin-Out Example ...

  • Page 36

    ... The ClockLock and ClockBoost features in ACEX 1K devices are enabled through the Altera software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins. ...

  • Page 37

    ... ACEX 1K Programmable Logic Device Family Data Sheet For designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to the GCLK1 pin. In the Altera software, the GCLK1 pin can feed both the ClockLock and ClockBoost circuitry in the ACEX 1K device. However, when both circuits are used, the other clock pin cannot be used. ClockLock & ...

  • Page 38

    ... Jitter on ClockLock or ClockBoost- JITTER generated clock (4) t Duty cycle for ClockLock or ClockBoost- OUTDUTY generated clock 38 and 12 summarize the ClockLock and ClockBoost parameters Condition t <100 INCLKSTB t < 50 INCLKSTB Min Typ Max Unit 180 MHz 16 90 MHz 25,000 PPM (2) 100 10 250 (4) 200 ( Altera Corporation ...

  • Page 39

    ... To implement the ClockLock and ClockBoost circuitry with the Altera software, designers must specify the input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The f parameter specifies how much the incoming clock can differ from the specified frequency during device CLKDEV operation ...

  • Page 40

    ... These devices have one set of V pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). 40 value and are required for 3.3-V PCI compliance. Clamping CCIO is CCIO is 2 pin CCIO CC Altera Corporation ...

  • Page 41

    ... Power Sequencing & Hot-Socketing Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet The VCCINT pins must always be connected to a 2.5-V power supply. With a 2.5-V V level, input voltages are compatible with 2.5-V, 3.3- CCINT V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5 ...

  • Page 42

    ... IDCODE information for ACEX 1K devices. 42 Table Table 15. ACEX 1K Boundary-Scan Register Length Device EP1K10 EP1K30 EP1K50 EP1K100 TM Standard Test and 14. Description Boundary-Scan Register Length 438 690 798 1,050 Tables 15 and 16 Altera Corporation ...

  • Page 43

    ... ACEX 1K devices include weak pull-up resistors on the JTAG pins. For more information, see the following documents: Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) ByteBlasterMV Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet Jam Programming & Test Language Specification Figure 20 shows the timing requirements for the JTAG signals ...

  • Page 44

    ... JTAG port valid output to high impedance JPXZ t Capture register setup time JSSU t Capture register hold time JSH t Update register clock to output JSCO t Update register high impedance to valid output JSZX t Update register valid output to high impedance JSXZ t JPH t JPXZ t JSXZ Min Max 100 Altera Corporation Unit ...

  • Page 45

    ... Ambient temperature AMB T Junction temperature J Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Each ACEX 1K device is functionally tested. Complete testing of each configurable static random access memory (SRAM) bit and all logic functionality ensures 100% yield. AC test measurements for ACEX 1K devices are made under conditions equivalent to those shown in Figure 21 ...

  • Page 46

    ... V CCIO 0 70 – –40 100 –40 125 40 40 Notes (6), (7) Typ Max 5.75 (8) CCIO 0.8, 0.3 V (8) CCIO 2.4 – 0.2 CCIO 2.1 2.0 1.7 Altera Corporation Unit ° C ° C ° C ° C ° Unit ...

  • Page 47

    ... Input pin leakage current I I Tri-stated I/O pin leakage OZ current I V supply current (standby) CC0 CC R Value of I/O pin pull-up CONF resistor before and during configuration Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Conditions Min DC 3.00 V (10) CCIO I = 0 3.00 V ...

  • Page 48

    ... Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial- and extended-temperature-range devices. ...

  • Page 49

    ... Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Figure 22 shows the required relationship between V satisfy 3.3-V PCI compliance. Figure 22. Relationship between V 2.7 V (V) CCINT II 2.5 2.3 3.0 Figure 23 shows the typical output drive characteristics of ACEX 1K devices with 3.3-V and 2.5 ...

  • Page 50

    ... 2.5 V CCINT Typical 2 CCIO Output Room Temperature Current (mA Output Voltage ( register clock-to-output delay (t Interconnect delay (t SAMEROW LE look-up table delay (t LE register setup time ( Room Temperature Output Voltage ( LUT ) 2.5 V CCINT = 3.3 V CCIO Altera Corporation ...

  • Page 51

    ... Figure 24. ACEX 1K Device Timing Model Dedicated Clock/Input Figure 25. ACEX 1K Device LE Timing Model Carry-In Data-In Control-In Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Figure 24 shows the overall timing model, which maps the possible paths to and from the various elements of the ACEX 1K device. Interconnect Logic ...

  • Page 52

    ... EABCH WDH t t EABCL WASU t WAH RASU t RAH Output Delays Delays t IOCO t OD1 t IOCOMB t OD2 t IOSU t OD3 t IOH IOCLR t ZX1 t ZX2 t ZX3 t INREG Output Register EAB Output Delays Delay t t EABCO EABOUT t EABBYPASS t EABSU t EABH t EABCH t EABCL Data-Out Altera Corporation ...

  • Page 53

    ... Clock Figure 29. EAB Asynchronous Timing Waveforms EAB Asynchronous Read WE a0 Address Data-Out d0 EAB Asynchronous Write WE Data-In t EABWASU a0 Address Data-Out Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet OE Register PRN D Q CLRN Output Register PRN D Q CLRN Input Register PRN D Q CLRN ...

  • Page 54

    ... Data-in to carry-out delay CGEN t LE register feedback to carry-out delay CGENR EABDATAH t EABDATACO din2 a2 t EABDATAH t EABDATASU t EABWCREG dout0 dout1 through 26 describe the ACEX 1K device internal timing Note (1) Parameter a2 t EABRCREG d1 din3 a3 t EABWEH t EABDATACO din1 din2 din3 Altera Corporation din2 Conditions ...

  • Page 55

    ... ZX3 t IOE input pad and buffer to IOE register delay INREG t IOE register feedback delay IOFD t IOE input pad and buffer to FastTrack Interconnect delay INCOMB Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Note (1) Parameter Note (1) Parameter = 3.3 V CCIO = 2.5 V CCIO = 3 ...

  • Page 56

    ... Address setup time before rising edge of read pulse RASU t Address hold time after falling edge of read pulse RAH t Write enable to data output valid delay WO t Data-in to data-out valid delay DD t Data-out delay EABOUT t Clock high time EABCH t Clock low time EABCL 56 Note (1) Parameter Conditions (5) (5) (5) (5) Altera Corporation ...

  • Page 57

    ... EAB address setup time before rising edge of write pulse when not using EABWASU input registers t EAB address hold time after falling edge of write pulse when not using input EABWAH registers t EAB write enable to data output valid delay EABWO Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Notes (1), (6) Parameter Conditions 13 57 ...

  • Page 58

    ... These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. 58 Note (1) Parameter = 3.3 V ± 10% for commercial or industrial and extended use in ACEX 1K devices = 2.5 V ± 5% for commercial or industrial and extended use in ACEX 1K devices 3.3 V. Conditions (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) Altera Corporation ...

  • Page 59

    ... Synchronous IOE output buffer enable delay, slow slew rate = off ZXBIDIR Notes to tables: (1) External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative subset of signal paths is tested to approximate typical device applications. (2) Contact Altera Applications for test circuit specifications and test conditions. ...

  • Page 60

    ... Note (1) -3 Min Max 0.8 1.1 0.6 0.8 0.7 1.0 0.4 0.5 1.0 1.3 0.1 0.2 0.5 0.7 0.1 0.2 0.9 1.1 1.3 1.7 0.7 0.9 0.5 0.7 1.0 1.1 1.0 1.4 1.0 1.4 2.5 2.5 Unit Altera Corporation ...

  • Page 61

    ... IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 2.6 0.3 0.9 0.0 1.5 1.0 1.1 3.1 2.6 5.8 3.8 3.8 3.3 6.5 3.7 ...

  • Page 62

    ... Unit Altera Corporation ...

  • Page 63

    ... EABWESU t 0.1 EABWEH t 1.6 EABWDSU t 0.0 EABWDH t 3.1 EABWASU t 0.6 EABWAH t EABWO Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 6.7 7.3 4.9 2.8 6.7 7.6 6.0 0.8 1.7 0.0 1.4 0.0 1.7 ...

  • Page 64

    ... Min Max 9.5 12.5 3.6 0.0 7.8 2.0 9.6 – 6.4 – – – 6.4 – 7.5 2.0 10.2 Unit Unit Altera Corporation ...

  • Page 65

    ... Table 37. EP1K30 Device LE Timing Microparameters (Part Symbol Min t LUT t CLUT t RLUT t PACKED CICO t CGEN t CGENR t CASC Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min 2.3 0.0 6.6 2.0 8.8 8.8 3.3 0.0 5.1 0.5 7.3 7.3 Tables 22 through 29 Tables 37 through 43 show EP1K30 device internal and external timing parameters ...

  • Page 66

    ... Note (1) -3 Min Max 2.8 3.8 0.4 0.5 1.1 1.6 0.0 0.0 1.9 0.5 1.1 1.6 2.3 3.0 1.8 2.5 5.2 7.0 3.1 4.3 3.1 4.3 2.6 3.8 6.0 8.3 4.1 5.5 1.3 2.4 1.3 2.4 Unit Unit Altera Corporation ...

  • Page 67

    ... WASU t 1.8 WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 2.5 EABCL Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 1.7 0.6 1.1 0.4 0.8 0.4 0.0 0.3 0.5 1.0 0.4 0.3 3.2 2.9 1 ...

  • Page 68

    ... Note (1) -3 Min Max 7.6 8.8 8.8 6.0 3.3 8.0 9.0 6.7 7.7 0.9 1.1 2.0 0.0 1.7 0.0 2.0 0.0 4.3 0.4 6.0 6.8 Unit Altera Corporation ...

  • Page 69

    ... INSU t (4) 0.0 INH t (4) 0.5 OUTCO t 3.0 PCISU t 0.0 PCIH t 2.0 PCICO Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 1.8 1.5 1.5 2.2 1.5 0.1 2.0 0.7 2.7 4.7 2.7 0.3 ...

  • Page 70

    ... Note (1) -3 Min Max 0.8 1.1 0.6 0.8 0.7 0.9 0.3 0.4 0.7 0.9 0.1 0.1 0.5 0.6 0.1 0.1 0.8 1.0 0.6 0.8 Unit Unit Altera Corporation ...

  • Page 71

    ... IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 0.6 0.3 0.6 0.6 0.4 0.8 2.5 2.5 Speed Grade -1 -2 Max Min Max 1.3 ...

  • Page 72

    ... Unit Altera Corporation ...

  • Page 73

    ... EABWESU t 0.4 EABWEH t 1.2 EABWDSU t 0.0 EABWDH t 1.6 EABWASU t 0.9 EABWAH t EABWO Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 3.7 5.2 4.9 2.8 6.3 7.8 3.8 0.8 1.6 0.0 1.0 0.6 1.7 ...

  • Page 74

    ... Min Max 9.5 12.5 3.9 0.0 5.2 2.0 7.3 – – 4.1 – – – – 7.7 – – Unit Unit Altera Corporation ...

  • Page 75

    ... Notes to tables: (1) All timing parameters are described in (2) This parameter is measured without use of the ClockLock or ClockBoost circuits. (3) This parameter is measured with use of the ClockLock or ClockBoost circuits Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 3 ...

  • Page 76

    ... Note (1) -3 Min Max 1.0 1.5 0.7 0.9 0.8 1.1 0.4 0.5 0.3 0.3 0.1 0.2 0.5 0.7 0.1 0.2 0.9 1.2 1.0 1.4 0.8 1.1 0.5 0.7 0.7 0.9 1.0 1.4 1.0 1.4 2.5 2.5 Unit Altera Corporation ...

  • Page 77

    ... IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 1.7 0.0 1.4 0.5 1.0 0.9 0.5 3.0 3.0 4.0 3.5 3.5 3.5 4.5 2.0 ...

  • Page 78

    ... Unit Altera Corporation ...

  • Page 79

    ... EABWESU t 0.0 EABWEH t 1.0 EABWDSU t 0.2 EABWDH t 4.1 EABWASU t 0.0 EABWAH t EABWO Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Speed Grade -1 -2 Max Min Max 5.9 7.6 6.5 3.5 7.7 7.0 3.4 0.5 1.0 0.1 1.4 0.0 1.3 ...

  • Page 80

    ... Min Max 16.0 3.3 0.0 6.9 2.0 9.1 – – 4.6 – – – – 6.9 – – Unit Unit Altera Corporation ...

  • Page 81

    ... This value is calculated based on the amount of current that each LE typically consumes. The P device output load characteristics and switching frequency, can be calculated using the guidelines given in Power for Altera Devices). 1 Compared to the rest of the device, the embedded array consumes a negligible amount of power. Therefore, the embedded array can be ignored when calculating supply current ...

  • Page 82

    ... This assumption may lead to inaccurate results when compared to measured power consumption for actual designs in segmented FPGAs. Figure 31 frequency of ACEX 1K devices. For information on other ACEX 1K devices, contact Altera Applications at (800) 800-EPLD. 82 value can be calculated with the following equation: CCACTIVE = K f ...

  • Page 83

    ... Figure 31. ACEX 1K I CCACTIVE EP1K30 100 80 Supply Current (mA Configuration & Operation Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet vs. Operating Frequency EP1K50 I CC Current (mA) 100 50 Frequency (MHz) EP1K100 300 200 Supply I CC Current (mA) 100 0 Frequency (MHz) The ACEX 1K architecture supports several configuration schemes. This section summarizes the device operating modes and available device configuration schemes ...

  • Page 84

    ... Configuration Scheme Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG Device Pin- See the Altera web site (http://www.altera.com) or the Altera Documen- tation Library for pin-out information. Outs 84 Table 59), chosen on the basis of the target Data Source ...

  • Page 85

    ... Revision History Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet The information contained in the ACEX 1K Programmable Logic Device Family Data Sheet version 3.4 supersedes information published in previous versions. The following changes were made to the ACEX 1K Programmable Logic Device Family Data Sheet version 3.4: added extended temperature support ...

  • Page 86

    ... Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...