IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 


Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
2
4
data[ ]
rdaddress[ ]
EAB Local
Interconnect (2)
wraddress[ ]
rden
wren
outclocken
inclocken
inclock
outclock
Notes:
(1)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2)
EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in
ACEX 1K EAB can also be used in a single-port mode (see
10
Note (1)
Row Interconnect
RAM/ROM
256
512
Data In
1,024
D
Q
2,048
ENA
Data Out
Read Address
D
Q
ENA
Write Address
D
Q
ENA
Read Enable
D
Q
ENA
Write Enable
D
Q
Multiplexers allow read
Write
ENA
address and read
Pulse
Generator
enable registers to be
clocked by inclock or
outclock signals.
4, 8, 16, 32
16
8
4
2
D
Q
4, 8
ENA
4, 8, 16, 32
Column Interconnect
Figure
3. The
Figure
4).
Altera Corporation