IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 


Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mode, the preset signal is tied to VCC to deactivate it.
Asynchronous Preset
An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide preset control by using the clear and inverting the
register’s input and output. Inversion control is available for the inputs to
both LEs and IOEs. Therefore, if a register is preset by only one of the two
LABCTRL signals, the DATA3 input is not needed and can be used for one
of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset, and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that
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asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear.
Altera Corporation
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