IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
t
Input rise time
R
t
Input fall time
F
t
Input duty cycle
INDUTY
f
Input clock frequency (ClockBoost clock
CLK1
multiplication factor equals 1)
f
Input clock frequency (ClockBoost clock
CLK2
multiplication factor equals 2)
f
Input deviation from user specification in
CLKDEV
the software
(1)
t
Input clock stability (measured between
INCLKSTB
adjacent clocks)
t
Time required for ClockLock or ClockBoost
LOCK
to acquire lock
(3)
t
Jitter on ClockLock or ClockBoost-
JITTER
generated clock
(4)
t
Duty cycle for ClockLock or ClockBoost-
OUTDUTY
generated clock
Notes to tables:
(1)
To implement the ClockLock and ClockBoost circuitry with the Altera software, designers must specify the input
frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
f
parameter specifies how much the incoming clock can differ from the specified frequency during device
CLKDEV
operation. Simulation does not reflect this parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t
(4)
The t
specification is measured under long-term observation. The maximum value for t
JITTER
t
is lower than 50 ps.
INCLKSTB
I/O
Configuration
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Condition
t
INCLKSTB
t
INCLKSTB
value is less than the time required for configuration.
LOCK
This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/O interface for
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via Altera software
logic options. The MultiVolt I/O interface is controlled by connecting
V
to a different voltage than V
CCIO
Altera software via the Global Project Device Options dialog box (Assign
menu).
Min
Typ
40
25
16
25,000
< 100
250
< 50
200
40
50
JITTER
. Its effect can be simulated in the
CCINT
Max
Unit
5
ns
5
ns
60
%
80
MHz
40
MHz
PPM
100
ps
10
s
(4)
ps
13
(4)
ps
60
%
is 200 ps if
39