IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
General
Altera
combining look-up table (LUT) architecture with EABs. LUT-based logic
Description
provides optimized performance and efficiency for data-path, register
intensive, mathematical, or digital signal processing (DSP) designs, while
EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO)
functions. These elements make ACEX 1K suitable for complex logic
functions and memory functions such as digital signal processing, wide
data-path manipulation, data transformation and microcontrollers, as
required in high-performance communications applications. Based on
reconfigurable CMOS SRAM elements, the ACEX 1K architecture
incorporates all features necessary to implement common gate array
megafunctions, along with a high pin count to enable an effective interface
with system components. The advanced process and the low voltage
requirement of the 2.5-V core allow ACEX 1K devices to meet the
requirements of low-cost, high-volume applications ranging from DSL
modems to low-cost switches.
The ability to reconfigure ACEX 1K devices enables complete testing prior
to shipment and allows the designer to focus on simulation and design
verification. ACEX 1K device reconfigurability eliminates inventory
management for gate array designs and test vector generation for fault
coverage.
Table 4
All performance results were obtained with Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 4. ACEX 1K Device Performance
Application
16-bit loadable counter
16-bit accumulator
16-to-1 multiplexer
(1)
16-bit multiplier with 3-stage
pipeline(2)
256
16 RAM read cycle speed
256
16 RAM write cycle speed
Notes:
(1)
This application uses combinatorial inputs and outputs.
(2)
This application uses registered inputs and outputs.
4
®
ACEX 1K devices provide a die-efficient, low-cost architecture by
shows ACEX 1K device performance for some common designs.
Resources
Used
LEs
EABs
16
0
16
0
10
0
592
0
(2)
0
1
(2)
0
1
Performance
Speed Grade
-1
-2
285
232
185
285
232
185
3.5
4.5
156
131
278
196
143
185
143
111
Altera Corporation
Units
-3
MHz
MHz
6.6
ns
93
MHz
MHz
MHz