IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 


Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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Power
Sequencing &
Hot-Socketing
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
The VCCINT pins must always be connected to a 2.5-V power supply.
With a 2.5-V V
level, input voltages are compatible with 2.5-V, 3.3-
CCINT
V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or
3.3-V power supply, depending on the output requirements. When the
VCCIO pins are connected to a 2.5-V power supply, the output levels are
compatible with 2.5-V systems. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with V
than 3.0 V achieve a faster timing delay of t
Table 13
summarizes ACEX 1K MultiVolt I/O support.
Table 13. ACEX 1K MultiVolt I/O Support
V
(V)
Input Signal (V)
CCIO
2.5
v
2.5
v
3.3
Notes:
(1)
The PCI clamping diode must be disabled on an input which is driven with a
voltage higher than V
.
CCIO
(2)
When V
= 3.3 V, an ACEX 1K device can drive a 2.5-V device that has 3.3-V
CCIO
tolerant inputs.
Open-drain output pins on ACEX 1K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a higher
V
than LVTTL. When the open-drain pin is active, it will drive low.
IH
When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby
meeting the CMOS V
requirement. The open-drain pin will only drive
OH
low or tri-state; it will never drive high. The rise time is dependent on the
value of the pull-up resistor and load impedance. The I
specification should be considered when selecting a pull-up resistor.
Because ACEX 1K devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The V
and V
CCIO
order.
Signals can be driven into ACEX 1K devices before and during power up
without damaging the device. Additionally, ACEX 1K devices do not
drive out during power up. Once operating conditions are reached,
ACEX 1K devices operate as specified by the user.
CCIO
instead of t
OD2
Output Signal (V)
3.3
5.0
2.5
v
v
v
(1)
(1)
v
v
v
(1)
(2)
power planes can be powered in any
CCINT
levels higher
.
OD1
3.3
5.0
v
v
13
current
OL
41