IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
IEEE Std.
All ACEX 1K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. ACEX 1K devices can also be
1149.1 (JTAG)
configured using the JTAG pins through the ByteBlasterMV or BitBlaster
download cable, or via hardware that uses the Jam
Boundary-Scan
Programming Language (STAPL), JEDEC standard JESD-71. JTAG
Support
boundary-scan testing can be performed before or after configuration, but
not during configuration. ACEX 1K devices support the JTAG
instructions shown in
Table 14. ACEX 1K JTAG Instructions
JTAG Instruction
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation and permits an initial data pattern to be output at the device
pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, allowing the BST data
to pass synchronously through a selected device to adjacent devices during normal
operation.
USERCODE
Selects the user electronic signature (USERCODE) register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
ICR Instructions
These instructions are used when configuring an ACEX 1K device via JTAG ports using
a MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or a Jam File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.
The instruction register length of ACEX 1K devices is 10 bits. The
USERCODE register length in ACEX 1K devices is 32 bits; 7 bits are
determined by the user, and 25 bits are pre-determined.
show the boundary-scan register length and device IDCODE information
for ACEX 1K devices.
42
Table
Table 15. ACEX 1K Boundary-Scan Register Length
Device
EP1K10
EP1K30
EP1K50
EP1K100
TM
Standard Test and
14.
Description
Boundary-Scan Register Length
438
690
798
1,050
Tables 15
and
16
Altera Corporation