IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
Figure 23. Output Drive Characteristics of ACEX 1K Devices
90
80
70
60
Typical I
O
50
Output
Current (mA)
40
30
20
10
V
Timing Model
The continuous, high-performance FastTrack Interconnect routing
resources ensure accurate simulation and timing analysis as well as
predictable performance. This predictable performance contrasts with
that of FPGAs, which use a segmented connection scheme and, therefore,
have an unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Timing simulation and delay prediction are available with the simulator
and Timing Analyzer, or with industry-standard EDA tools. The
Simulator offers both pre-synthesis functional simulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
50
I
OL
V
= 2.5
V
CCINT
Typical I
V
= 2.5
V
O
CCIO
Output
Room Temperature
Current (mA)
I
OH
1
2
3
Output Voltage (V)
O
LE register clock-to-output delay (t
Interconnect delay (t
SAMEROW
LE look-up table delay (t
LE register setup time (t
90
I
80
70
60
V
V
50
Room Temperature
40
30
20
10
1
2
V
Output Voltage (V)
O
)
CO
)
)
LUT
)
SU
OL
= 2.5
V
CCINT
= 3.3
V
CCIO
I
OH
3
Altera Corporation