EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 55

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027
Table 22. LE Timing Microparameters (Part 2 of 2)
Symbol
t
Cascade-in to cascade-out delay
CASC
t
LE register control signal delay
C
t
LE register clock-to-output delay
CO
t
Combinatorial delay
COMB
t
LE register setup time for data and enable signals before clock; LE register
SU
recovery time after asynchronous clear, preset, or load
t
LE register hold time for data and enable signals after clock
H
t
LE register preset delay
PRE
t
LE register clear delay
CLR
t
Minimum clock high time from clock pin
CH
t
Minimum clock low time from clock pin
CL
Table 23. IOE Timing Microparameters
Symbol
t
IOE data delay
IOD
t
IOE register control signal delay
IOC
t
IOE register clock-to-output delay
IOCO
t
IOE combinatorial delay
IOCOMB
t
IOE register setup time for data and enable signals before clock; IOE register
IOSU
recovery time after asynchronous clear
t
IOE register hold time for data and enable signals after clock
IOH
t
IOE register clear time
IOCLR
t
Output buffer and pad delay, slow slew rate = off, V
OD1
t
Output buffer and pad delay, slow slew rate = off, V
OD2
t
Output buffer and pad delay, slow slew rate = on
OD3
t
IOE output buffer disable delay
XZ
t
IOE output buffer enable delay, slow slew rate = off, V
ZX1
t
IOE output buffer enable delay, slow slew rate = off, V
ZX2
t
IOE output buffer enable delay, slow slew rate = on
ZX3
t
IOE input pad and buffer to IOE register delay
INREG
t
IOE register feedback delay
IOFD
t
IOE input pad and buffer to FastTrack Interconnect delay
INCOMB
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Note (1)
Parameter
Note (1)
Parameter
= 3.3 V
CCIO
= 2.5 V
CCIO
= 3.3 V
CCIO
= 2.5 V
CCIO
Conditions
13
Conditions
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
55

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