EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 56

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027
ACEX 1K Programmable Logic Device Family Data Sheet
Table 24. EAB Timing Microparameters
Symbol
t
Data or address delay to EAB for combinatorial input
EABDATA1
t
Data or address delay to EAB for registered input
EABDATA2
t
Write enable delay to EAB for combinatorial input
EABWE1
t
Write enable delay to EAB for registered input
EABWE2
t
Read enable delay to EAB for combinatorial input
EABRE1
t
Read enable delay to EAB for registered input
EABRE2
t
EAB register clock delay
EABCLK
t
EAB register clock-to-output delay
EABCO
t
Bypass register delay
EABBYPASS
t
EAB register setup time before clock
EABSU
t
EAB register hold time after clock
EABH
t
EAB register asynchronous clear time to output delay
EABCLR
t
Address access delay (including the read enable to output delay)
AA
t
Write pulse width
WP
t
Read pulse width
RP
t
Data setup time before falling edge of write pulse
WDSU
t
Data hold time after falling edge of write pulse
WDH
t
Address setup time before rising edge of write pulse
WASU
t
Address hold time after falling edge of write pulse
WAH
t
Address setup time before rising edge of read pulse
RASU
t
Address hold time after falling edge of read pulse
RAH
t
Write enable to data output valid delay
WO
t
Data-in to data-out valid delay
DD
t
Data-out delay
EABOUT
t
Clock high time
EABCH
t
Clock low time
EABCL
56
Note (1)
Parameter
Conditions
(5)
(5)
(5)
(5)
Altera Corporation

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