EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 8

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 1. ACEX 1K Device Block Diagram
8
Row
Interconnect
I/O Element
(IOE)
Column
Interconnect
Logic
Array
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
ACEX 1K devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.0 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
IOE
IOE
IOE
IOE
IOE
IOE
Embedded Array Block (EAB)
IOE
IOE
Embedded Array
EAB
EAB
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Altera Corporation
IOE
IOE
IOE
IOE
Logic Array
Block (LAB)
Logic Array
Local Interconnect
Logic Element (LE)

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