EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 83

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027
Figure 31. ACEX 1K I
CCACTIVE
EP1K30
100
80
Supply
I
60
CC
Current (mA)
40
20
0
Configuration &
Operation
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
vs. Operating Frequency
EP1K50
I
CC
Current (mA)
100
50
Frequency (MHz)
EP1K100
300
200
Supply
I
CC
Current (mA)
100
0
Frequency (MHz)
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as V
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50 s.
1
When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
200
150
Supply
100
50
0
50
Frequency (MHz)
100
50
rises, the device initiates a
CC
100
13
83

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