EP1C3T100I7N | |
|---|---|
| Manufacturer Part Number | EP1C3T100I7N |
| Description | IC CYCLONE FPGA 2910 LE 100-TQFP |
| Manufacturer | Altera |
| Series | Cyclone® |
| EP1C3T100I7N datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of EP1C3T100I7N | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 2910 | Number Of Labs/clbs | 291 |
| Total Ram Bits | 59904 | Number Of I /o | 65 |
| Voltage - Supply | 1.425 V ~ 1.575 V | Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 100°C | Package / Case | 100-TQFP, 100-VQFP |
| Family Name | Cyclone® | Number Of Logic Blocks/elements | 2910 |
| # I/os (max) | 65 | Frequency (max) | 320.1MHz |
| Process Technology | 0.13um (CMOS) | Operating Supply Voltage (typ) | 1.5V |
| Logic Cells | 2910 | Ram Bits | 59904 |
| Operating Supply Voltage (min) | 1.425V | Operating Supply Voltage (max) | 1.575V |
| Operating Temp Range | -40C to 100C | Operating Temperature Classification | Industrial |
| Mounting | Surface Mount | Pin Count | 100 |
| Package Type | TQFP | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Number Of Gates | - | Other names | 544-1663 |
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PrevNext
Cyclone Device Handbook, Volume 1
Table 1–1. Cyclone Device Features (Part 2 of 2)
Feature
Total RAM bits
PLLs
Maximum user I/O pins
(1)
Note to
Table
1–1:
(1)
This parameter includes global clock pins.
Cyclone devices are available in quad flat pack (QFP) and space-saving
FineLine
Table 1–2. Cyclone Package Options and I/O Pin Counts
100-Pin TQFP
144-Pin TQFP
Device
(1)
EP1C3
65
EP1C4
—
EP1C6
—
EP1C12
—
EP1C20
—
Notes to
Table
1–2:
(1)
TQFP: thin quad flat pack.
PQFP: plastic quad flat pack.
(2)
Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the
EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).
Vertical migration means you can migrate a design from one device to
another that has the same dedicated pins, JTAG pins, and power pins, and
are subsets or supersets for a given package across device densities. The
largest density in any package has the highest number of power pins; you
must use the layout for the largest planned density in a package to
provide the necessary power pins for migration.
For I/O pin migration across densities, cross-reference the available I/O
pins using the device pin-outs for all planned densities of a given package
type to identify which I/O pins can be migrated. The Quartus
software can automatically cross-reference and place all pins for you
when given a device migration list. If one device has power or ground
pins, but these same pins are user I/O on a different device that is in the
migration path,the Quartus II software ensures the pins are not used as
user I/O in the Quartus II software. Ensure that these pins are connected
1–2
Preliminary
EP1C3
EP1C4
59,904
78,336
1
2
104
301
®
BGA packages (see
Tables 1–2
240-Pin PQFP
256-Pin
(1),
(2)
(1)
FineLine BGA
104
—
—
—
98
185
185
—
173
185
—
—
EP1C6
EP1C12
EP1C20
92,160
239,616
294,912
2
2
2
185
249
301
through 1–3).
324-Pin
400-Pin
FineLine BGA
FineLine BGA
—
—
—
—
249
301
—
—
249
—
—
233
301
®
II
Altera Corporation
May 2008
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