IC CYCLONE FPGA 2910 LE 100-TQFP

 

EP1C3T100I7N

Manufacturer Part NumberEP1C3T100I7N
DescriptionIC CYCLONE FPGA 2910 LE 100-TQFP
ManufacturerAltera
SeriesCyclone®
EP1C3T100I7N datasheets

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Specifications of EP1C3T100I7N

Number Of Logic Elements/cells2910Number Of Labs/clbs291
Total Ram Bits59904Number Of I /o65
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case100-TQFP, 100-VQFP
Family NameCyclone®Number Of Logic Blocks/elements2910
# I/os (max)65Frequency (max)320.1MHz
Process Technology0.13um (CMOS)Operating Supply Voltage (typ)1.5V
Logic Cells2910Ram Bits59904
Operating Supply Voltage (min)1.425VOperating Supply Voltage (max)1.575V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count100
Package TypeTQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1663
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Figure 2–28. Row I/O Block Connection to the Interconnect
R4 Interconnects
LAB
Direct Link
Interconnect
to Adjacent LAB
LAB Local
Interconnect
Notes to
Figure
2–28:
The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
(1)
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one
(2)
comb_io_datain (combinatorial) input.
Altera Corporation
May 2008
C4 Interconnects
I/O Block Local
Interconnect
21
io_datain[2..0] and
comb_io_datain[2..0] (2)
Direct Link
Interconnect
from Adjacent LAB
io_clk[5:0]
I/O Structure
21 Data and
Control Signals
from Logic Array (1)
Row
I/O Block
Row I/O Block
Contains up to
Three IOEs
2–41
Preliminary

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