IC CYCLONE FPGA 2910 LE 100-TQFP

 

EP1C3T100I7N

Manufacturer Part NumberEP1C3T100I7N
DescriptionIC CYCLONE FPGA 2910 LE 100-TQFP
ManufacturerAltera
SeriesCyclone®
EP1C3T100I7N datasheets

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Specifications of EP1C3T100I7N

Number Of Logic Elements/cells2910Number Of Labs/clbs291
Total Ram Bits59904Number Of I /o65
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case100-TQFP, 100-VQFP
Family NameCyclone®Number Of Logic Blocks/elements2910
# I/os (max)65Frequency (max)320.1MHz
Process Technology0.13um (CMOS)Operating Supply Voltage (typ)1.5V
Logic Cells2910Ram Bits59904
Operating Supply Voltage (min)1.425VOperating Supply Voltage (max)1.575V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count100
Package TypeTQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1663
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Cyclone Device Handbook, Volume 1
Table 2–10. DQ Pin Groups (Part 2 of 2)
Device
EP1C6
EP1C12
EP1C20
Note to
(1)
A programmable delay chain on each DQS pin allows for either a 90°
phase shift (for DDR SDRAM), or a 72° phase shift (for FCRAM) which
automatically center-aligns input DQS synchronization signals within the
data window of their corresponding DQ data signals. The phase-shifted
DQS signals drive the global clock network. This global DQS signal clocks
DQ signals on internal LE registers.
These DQS delay elements combine with the PLL’s clocking and phase
shift ability to provide a complete hardware solution for interfacing to
high-speed memory.
The clock phase shift allows the PLL to clock the DQ output enable and
output paths. The designer should use the following guidelines to meet
133 MHz performance for DDR SDRAM and FCRAM interfaces:
■
■
■
Figure 2–34
I/O through the dedicated circuitry to the logic array.
2–48
Preliminary
Package
144-pin TQFP
240-pin PQFP
256-pin FineLine BGA
240-pin PQFP
256-pin FineLine BGA
324-pin FineLine BGA
324-pin FineLine BGA
400-pin FineLine BGA
Table
2–10:
EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in
I/O bank 1.
The DQS signal must be in the middle of the DQ group it clocks
Resynchronize the incoming data to the logic array clock using
successive LE registers or FIFO buffers
LE registers must be placed in the LAB adjacent to the DQ I/O pin
column it is fed by
illustrates DDR SDRAM and FCRAM interfacing from the
Number of × 8 DQ
Total DQ Pin
Pin Groups
Count
4
32
4
32
4
32
4
32
4
32
8
64
8
64
8
64
Altera Corporation
May 2008

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