IC CYCLONE FPGA 2910 LE 100-TQFP

 

EP1C3T100I7N

Manufacturer Part NumberEP1C3T100I7N
DescriptionIC CYCLONE FPGA 2910 LE 100-TQFP
ManufacturerAltera
SeriesCyclone®
EP1C3T100I7N datasheets

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Specifications of EP1C3T100I7N

Number Of Logic Elements/cells2910Number Of Labs/clbs291
Total Ram Bits59904Number Of I /o65
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case100-TQFP, 100-VQFP
Family NameCyclone®Number Of Logic Blocks/elements2910
# I/os (max)65Frequency (max)320.1MHz
Process Technology0.13um (CMOS)Operating Supply Voltage (typ)1.5V
Logic Cells2910Ram Bits59904
Operating Supply Voltage (min)1.425VOperating Supply Voltage (max)1.575V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count100
Package TypeTQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1663
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Figure 2–34. DDR SDRAM and FCRAM Interfacing
OE LE
OE
Register
Output LE
OE LE
Register
Register
V
CC
Output LE
Register
GND
PLL
Phase Shifted -90˚
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the I
Altera Corporation
May 2008
DQS
OE
OE LE
Register
Δ t
clk
OE LE
DataA
Register
DataB
Programmable
Delay Chain
Global Clock
I/O Structure
DQ
Output LE
Registers
Input LE
Adjacent
Registers
LAB LEs
-90˚ clk
Output LE
Registers
Input LE
Registers
LE
Register
LE
Register
Resynchronizing
Global Clock
Adjacent LAB LEs
OH
Preliminary
/I
OL
2–49

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