IC CYCLONE FPGA 2910 LE 100-TQFP

 

EP1C3T100I7N

Manufacturer Part NumberEP1C3T100I7N
DescriptionIC CYCLONE FPGA 2910 LE 100-TQFP
ManufacturerAltera
SeriesCyclone®
EP1C3T100I7N datasheets

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Specifications of EP1C3T100I7N

Number Of Logic Elements/cells2910Number Of Labs/clbs291
Total Ram Bits59904Number Of I /o65
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case100-TQFP, 100-VQFP
Family NameCyclone®Number Of Logic Blocks/elements2910
# I/os (max)65Frequency (max)320.1MHz
Process Technology0.13um (CMOS)Operating Supply Voltage (typ)1.5V
Logic Cells2910Ram Bits59904
Operating Supply Voltage (min)1.425VOperating Supply Voltage (max)1.575V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count100
Package TypeTQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1663
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Cyclone Device Handbook, Volume 1
Table 3–1. Cyclone JTAG Instructions (Part 2 of 2)
JTAG Instruction
Instruction Code
USERCODE
00 0000 0111
IDCODE
00 0000 0110
HIGHZ
(1)
00 0000 1011
CLAMP
(1)
00 0000 1010
ICR instructions
—
PULSE_NCONFIG
00 0000 0001
CONFIG_IO
00 0000 1101
SignalTap II
—
instructions
Note to
Table
3–1:
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(1)
In the Quartus II software, there is an Auto Usercode feature where you
can choose to use the checksum value of a programming file as the JTAG
user code. If selected, the checksum is automatically loaded to the
USERCODE register. Choose Assignments > Device > Device and Pin
Options > General. Turn on Auto Usercode.
3–2
Preliminary
Description
Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring a Cyclone device via the JTAG port with a
TM
TM
MasterBlaster
or ByteBlasterMV
using a Jam File or Jam Byte-Code File via an embedded
processor.
nCONFIG
Emulates pulsing the
pin low to trigger reconfiguration
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if executed during configuration.
CONFIG_IO
Once issued, the
instruction will hold
nSTATUS
to reset the configuration device.
device is reconfigured.
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
download cable, or when
nSTATUS
low
is held low until the
Altera Corporation
May 2008

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