EP1C3T100I7N | |
|---|---|
| Manufacturer Part Number | EP1C3T100I7N |
| Description | IC CYCLONE FPGA 2910 LE 100-TQFP |
| Manufacturer | Altera |
| Series | Cyclone® |
| EP1C3T100I7N datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of EP1C3T100I7N | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 2910 | Number Of Labs/clbs | 291 |
| Total Ram Bits | 59904 | Number Of I /o | 65 |
| Voltage - Supply | 1.425 V ~ 1.575 V | Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 100°C | Package / Case | 100-TQFP, 100-VQFP |
| Family Name | Cyclone® | Number Of Logic Blocks/elements | 2910 |
| # I/os (max) | 65 | Frequency (max) | 320.1MHz |
| Process Technology | 0.13um (CMOS) | Operating Supply Voltage (typ) | 1.5V |
| Logic Cells | 2910 | Ram Bits | 59904 |
| Operating Supply Voltage (min) | 1.425V | Operating Supply Voltage (max) | 1.575V |
| Operating Temp Range | -40C to 100C | Operating Temperature Classification | Industrial |
| Mounting | Surface Mount | Pin Count | 100 |
| Package Type | TQFP | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Number Of Gates | - | Other names | 544-1663 |
PrevNext
Table 4–20. Cyclone Device Performance
Resource
Design Size and
Used
Function
M4K
RAM 128 × 36 bit Single port
memory
RAM 128 × 36 bit Simple
block
dual-port
mode
RAM 256 × 18 bit True dual-
port mode
FIFO 128 × 36 bit
Shift register
Shift
9 × 4 × 128
register
Note to
Table
4–20:
(1)
The performance numbers for this function are from an EP1C6 device in a 240-pin PQFP package.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density.
Cyclone device internal timing microparameters for LEs, IOEs, M4K
memory structures, and MultiTrack interconnects.
Table 4–21. LE Internal Timing Microparameter Descriptions
t
SU
t
H
t
CO
t
LUT
t
CLR
t
PRE
t
CLKHL
Altera Corporation
May 2008
Resources Used
M4K
M4K
Mode
LEs
Memory
Memory
Bits
Blocks
—
4,608
—
4,608
—
4,608
—
40
4,608
11
4,536
Tables 4–21
Symbol
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinatorial LUT delay for data-in to data-out
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
Timing Model
Performance
-6 Speed
-7 Speed
-8 Speed
Grade
Grade
Grade
(MHz)
(MHz)
(MHz)
1
256.00
222.67
197.01
1
255.95
222.67
196.97
1
255.95
222.67
196.97
1
256.02
222.67
197.01
1
255.95
222.67
196.97
through
4–24
describe the
Parameter
Preliminary
4–11
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