EP1C3T100I7N | |
|---|---|
| Manufacturer Part Number | EP1C3T100I7N |
| Description | IC CYCLONE FPGA 2910 LE 100-TQFP |
| Manufacturer | Altera |
| Series | Cyclone® |
| EP1C3T100I7N datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of EP1C3T100I7N | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 2910 | Number Of Labs/clbs | 291 |
| Total Ram Bits | 59904 | Number Of I /o | 65 |
| Voltage - Supply | 1.425 V ~ 1.575 V | Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 100°C | Package / Case | 100-TQFP, 100-VQFP |
| Family Name | Cyclone® | Number Of Logic Blocks/elements | 2910 |
| # I/os (max) | 65 | Frequency (max) | 320.1MHz |
| Process Technology | 0.13um (CMOS) | Operating Supply Voltage (typ) | 1.5V |
| Logic Cells | 2910 | Ram Bits | 59904 |
| Operating Supply Voltage (min) | 1.425V | Operating Supply Voltage (max) | 1.575V |
| Operating Temp Range | -40C to 100C | Operating Temperature Classification | Industrial |
| Mounting | Surface Mount | Pin Count | 100 |
| Package Type | TQFP | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Number Of Gates | - | Other names | 544-1663 |
PrevNext
Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters
Symbol
t
I N S U
t
I N H
t
O U T C O
t
X Z
t
Z X
t
I N S U P L L
t
I N H P L L
t
O U T C O P L L
t
X Z P L L
t
Z X P L L
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density.
Tables 4–40
and row I/O pins for all packages. If an I/O standard is selected other
than LVTTL 4 mA with a fast slew rate, add the selected delay to the
external t
4–28.
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
-6 Speed Grade
I/O Standard
Min
LVCMOS
—
3.3-V LVTTL
—
2.5-V LVTTL
—
1.8-V LVTTL
—
1.5-V LVTTL
—
SSTL-3 class I
—
SSTL-3 class II
—
SSTL-2 class I
—
Altera Corporation
May 2008
-6 Speed Grade
-7 Speed Grade
Min
Max
Min
2.417
—
2.779
0.000
—
0.000
2.000
3.724
2.000
—
3.645
—
—
3.645
—
1.417
—
1.629
0.000
—
0.000
0.500
1.667
0.500
—
1.588
—
—
1.588
—
through
4–45
show the adder delays associated with column
and t
I/O parameters shown in
CO
SU
-7 Speed Grade
Max
Min
Max
0
—
0
0
—
0
27
—
31
182
—
209
278
—
319
–250
—
–288
–250
—
–288
–278
—
–320
Timing Model
-8 Speed Grade
Unit
Max
Min
Max
—
3.140
—
ns
—
0.000
—
ns
4.282
2.000
4.843
ns
4.191
—
4.740
ns
4.191
—
4.740
ns
—
1.840
—
ns
—
0.000
—
ns
1.917
0.500
2.169
ns
1.826
—
2.066
ns
1.826
—
2.066
ns
Tables 4–25
through
-8 Speed Grade
Unit
Min
Max
—
0
ps
—
0
ps
—
35
ps
—
236
ps
—
361
ps
—
–325
ps
—
–325
ps
—
–362
ps
4–21
Preliminary
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IC CYCLONE FPGA 2910 LE 100-TQFP | Altera |
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IC CYCLONE FPGA 2910 LE 100-TQFP | Altera |
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Altera Corporation | ||

