EP1C3T100I7N | |
|---|---|
| Manufacturer Part Number | EP1C3T100I7N |
| Description | IC CYCLONE FPGA 2910 LE 100-TQFP |
| Manufacturer | Altera |
| Series | Cyclone® |
| EP1C3T100I7N datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of EP1C3T100I7N | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 2910 | Number Of Labs/clbs | 291 |
| Total Ram Bits | 59904 | Number Of I /o | 65 |
| Voltage - Supply | 1.425 V ~ 1.575 V | Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 100°C | Package / Case | 100-TQFP, 100-VQFP |
| Family Name | Cyclone® | Number Of Logic Blocks/elements | 2910 |
| # I/os (max) | 65 | Frequency (max) | 320.1MHz |
| Process Technology | 0.13um (CMOS) | Operating Supply Voltage (typ) | 1.5V |
| Logic Cells | 2910 | Ram Bits | 59904 |
| Operating Supply Voltage (min) | 1.425V | Operating Supply Voltage (max) | 1.575V |
| Operating Temp Range | -40C to 100C | Operating Temperature Classification | Industrial |
| Mounting | Surface Mount | Pin Count | 100 |
| Package Type | TQFP | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Number Of Gates | - | Other names | 544-1663 |
PrevNext
Table 4–47. Cyclone IOE Programmable Delays on Row Pins
Parameter
Setting
Decrease input delay to
Off
internal cells
Small
Medium
Large
On
Decrease input delay to input
Off
register
On
Increase delay to output pin
Off
On
Note to
Table
4–47:
(1)
EPC1C3 devices do not support the PCI I/O standard.
Maximum Input and Output Clock Rates
Tables 4–48
row pins in Cyclone devices.
Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Altera Corporation
May 2008
-6 Speed Grade
-7 Speed Grade
Min
Max
Min
—
154
—
—
2,212
—
—
2,639
—
—
3,057
—
—
154
—
—
0
—
—
3,057
—
—
0
—
—
556
—
and
4–49
show the maximum input clock rate for column and
-6 Speed
I/O Standard
Grade
464
392
387
387
405
405
414
464
473
567
Timing Model
-8 Speed Grade
Unit
Max
Min
Max
177
—
200
ps
2,543
—
2,875
ps
3,034
—
3,430
ps
3,515
—
3,974
ps
177
—
200
ps
0
—
0
ps
3,515
—
3,974
ps
0
—
0
ps
639
—
722
ps
-7 Speed
-8 Speed
Unit
Grade
Grade
428
387
MHz
302
207
MHz
311
252
MHz
320
243
MHz
374
333
MHz
356
293
MHz
365
302
MHz
428
396
MHz
432
396
MHz
549
531
MHz
4–27
Preliminary
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IC CYCLONE FPGA 2910 LE 100-TQFP | Altera |
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IC CYCLONE FPGA 2910 LE 100-TQFP | Altera |
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IC CYCLONE FPGA 2910 LE 100-TQFP | Altera |
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Altera Corporation | ||
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Altera Corporation |
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Altera Corporation | ||

