EP2C8Q208C8N Altera, EP2C8Q208C8N Datasheet - Page 120

• Manufacturer Part Number: EP2C8Q208C8N
• Description: IC CYCLONE II FPGA 8K 208-PQFP
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C8Q208C8N

• Number Of Logic Elements/cells: 8256
• Number Of Labs/clbs: 516
• Total Ram Bits: 165888
• Number Of I /o: 138
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 8256
• # I/os (max): 138
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 8256
• Ram Bits: 165888
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1671

Timing Specifications
5–30
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
Input Delay
from Pin to
Internal
Cells
Input Delay
from Pin to
Input
Register
Delay from
Output
Register to
Output Pin
Input Delay
from Pin to
Internal
Cells
Parameter
Parameter Paths Affected
Table 5–36. Cyclone II IOE Programmable Delay on Column Pins
Table 5–37. Cyclone II IOE Programmable Delay on Row Pins
The incremental values for the settings are generally linear. For exact values of each setting, use the latest version
of the Quartus II software.
The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II
software.
The value in the first row for each parameter represents the fast corner timing parameter for industrial and
automotive devices. The second row represents the fast corner timing parameter for commercial devices.
The value in the first row is for automotive devices. The second row is for commercial devices.
Table
Pad ->
I/O
dataout
to core
Pad -> I/O
dataout to core
Pad -> I/O
input register
I/O output
register -> Pad
Affected
Paths
5–36:
Settings
Number
of
7
IOE Programmable Delay
Refer to
Settings
Number
of
7
8
2
Fast Corner
Offset
Min
0
0
Table 5–36
Offset
Fast Corner
Min
0
0
0
0
0
0
Offset
2240
2352
Max
(3)
(3)
Offset
2233
2344
2656
2788
Max
303
318
and
Offset
Min
—
0
–6 Speed
5–37
Offset
Grade
Min
—
—
—
–6 Speed
0
0
0
Grade
Offset
for IOE programmable delay.
3776
Max
—
Offset
3827
4555
Notes
Max
563
—
—
—
Notes
Offset
Min
(1),
Offset
0
0
–7 Speed
Grade
Min
–7 Speed
0
0
0
0
0
0
(1),
(2)
Grade
(4)
Offset
(4)
4174
4033
(2)
Max
(Part 1 of 2)
Offset
4232
4088
4914
4748
Max
638
617
–8 Speed Grade
Offset
Offset
Min
Min
—
—
—
—
0
Altera Corporation
–8 Speed
0
0
0
Grade
February 2008
Offset
Offset
4349
4940
4290
Max
Max
670
—
—
—
—
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps