EP2C8Q208C8N Altera, EP2C8Q208C8N Datasheet - Page 58

IC CYCLONE II FPGA 8K 208-PQFP

EP2C8Q208C8N

Manufacturer Part Number
EP2C8Q208C8N
Description
IC CYCLONE II FPGA 8K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C8Q208C8N

Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
138
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
138
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1671

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I/O Structure & Features
Figure 2–26. Cyclone II Device DQ & DQS Groups in ×8/×9 Mode
Notes to
(1)
(2)
2–46
Cyclone II Device Handbook, Volume 1
EP2C5
EP2C8
EP2C15
EP2C20
Table 2–15. Cyclone II DQS & DQ Bus Mode Support (Part 1 of 2)
Device
Each DQ group consists of a DQS pin, DM pin, and up to nine DQ pins.
This is an idealized pin layout. For actual pin layout, refer to the pin table.
Figure
2–26:
144-pin TQFP
208-pin PQFP
144-pin TQFP
208-pin PQFP
256-pin FineLine BGA
256-pin FineLine BGA
484-pin FineLine BGA
256-pin FineLine BGA
484-pin FineLine BGA
DQ Pins
Package
Cyclone II devices support the data strobe or read clock signal (DQS)
used in DDR and DDR2 SDRAM. Cyclone II devices can use either
bidirectional data strobes or unidirectional read clocks. The dedicated
external memory interface in Cyclone II devices also includes
programmable delay circuitry that can shift the incoming DQS signals to
center align the DQS signals within the data window.
The DQS signal is usually associated with a group of data (DQ) pins. The
phase-shifted DQS signals drive the global clock network, which is used
to clock the DQ signals on internal LE registers.
Table 2–15
(2)
(2)
®
shows the number of DQ pin groups per device.
Number of ×8
Groups
16
16
7
7
8
3
3
8
8
(3)
(3)
(3)
(4)
(4)
DQS Pin
Groups (5),
(2)
Number of ×9
3
4
3
4
4
4
8
4
8
Notes
(6)
Note (1)
(1),
DQ Pins
Number of ×16
(2)
Groups
0
3
0
3
4
4
8
4
8
Altera Corporation
Number of ×18
Groups (5),
February 2007
DM Pin
0
3
0
3
4
4
8
4
8
(6)

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