IC CYCLONE FPGA 20K LE 324-FBGA

 

EP1C20F324C7N

Manufacturer Part NumberEP1C20F324C7N
DescriptionIC CYCLONE FPGA 20K LE 324-FBGA
ManufacturerAltera
SeriesCyclone®
EP1C20F324C7N datasheets

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Specifications of EP1C20F324C7N

Number Of Logic Elements/cells20060Number Of Labs/clbs2006
Total Ram Bits294912Number Of I /o233
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case324-FBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
Other names544-1678  
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C51003-1.4
IEEE Std. 1149.1
All Cyclone
IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be
(JTAG) Boundary
performed either before or after, but not during configuration. Cyclone
Scan Support
devices can also use the JTAG port for configuration together with either
the Quartus
Byte-Code Files (.jbc).
Cyclone devices support reconfiguring the I/O standard settings on the
IOE through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode. Designers can use this ability for JTAG testing before configuration
when some of the Cyclone pins drive or receive from other devices on the
board using voltage-referenced standards. Since the Cyclone device
might not be configured before JTAG testing, the I/O pins might not be
configured for appropriate electrical standards for chip-to-chip
communication. Programming those I/O standards via JTAG allows
designers to fully test I/O connection to other devices.
The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The
TDO pin voltage is determined by the V
The bank V
3.3-V compatible.
Cyclone devices also use the JTAG port to monitor the operation of the
device with the SignalTap
support the JTAG instructions shown in
Table 3–1. Cyclone JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
SAMPLE
PRELOAD
00 0000 0101
/
EXTEST
(1)
00 0000 0000
BYPASS
11 1111 1111
Altera Corporation
May 2008
3. Configuration and Testing
®
devices provide JTAG BST circuitry that complies with the
®
II software or hardware using either Jam Files (.jam) or Jam
CCIO
selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or
CCIO
®
II embedded logic analyzer. Cyclone devices
Table
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
of the bank where it resides.
3–1.
3–1
Preliminary

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