EPF10K30RI208-4 Altera, EPF10K30RI208-4 Datasheet - Page 27
Manufacturer Part Number
IC FLEX 10K FPGA 30K 208-RQFP
Specifications of EPF10K30RI208-4
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Number Of Gates
Voltage - Supply
4.5 V ~ 5.5 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For improved routing, the row interconnect is comprised of a combination
of full-length and half-length channels. The full-length channels connect
to all LABs in a row; the half-length channels connect to the LABs in half
of the row. The EAB can be driven by the half-length channels in the left
half of the row and by the full-length channels. The EAB drives out to the
full-length channels. In addition to providing a predictable, row-wide
interconnect, this architecture provides increased routing resources. Two
neighboring LABs can be connected using a half-row channel, thereby
saving the other half of the channel for the other half of the row.
each FLEX 10K device.
In addition to general-purpose I/O pins, FLEX 10K devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output enable and clock enable control signals. These signals
are available as control signals for all LABs and IOEs in the device.
The dedicated inputs can also be used as general-purpose data inputs
because they can feed the local interconnect of each LAB in the device.
However, the use of dedicated inputs as data inputs can introduce
additional delay into the control signal network.
Table 7. FLEX 10K FastTrack Interconnect Resources
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
summarizes the FastTrack Interconnect resources available in