IC FLEX 10K FPGA 30K 208-RQFP

EPF10K30RI208-4

Manufacturer Part NumberEPF10K30RI208-4
DescriptionIC FLEX 10K FPGA 30K 208-RQFP
ManufacturerAltera
SeriesFLEX-10K®
EPF10K30RI208-4 datasheet
 


Specifications of EPF10K30RI208-4

Number Of Logic Elements/cells1728Number Of Labs/clbs216
Total Ram Bits12288Number Of I /o147
Number Of Gates69000Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case208-RQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2233  
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Notes to tables:
(1)
FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),
TM
and FineLine BGA
packages.
(2)
This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine
BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin
FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set.
General
Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based
on reconfigurable CMOS SRAM elements, the Flexible Logic Element
Description
MatriX (FLEX) architecture incorporates all features necessary to
implement common gate array megafunctions. With up to 250,000 gates,
the FLEX 10K family provides the density, speed, and features to integrate
entire systems, including multiple 32-bit buses, into a single device.
FLEX 10K devices are reconfigurable, which allows 100
shipment. As a result, the designer is not required to generate test vectors
for fault coverage purposes. Additionally, the designer does not need to
manage inventories of different ASIC designs; FLEX 10K devices can be
configured on the board for the specific functionality required.
Table 6
performance values were obtained with Synopsys DesignWare or LPM
functions. No special design technique was required to implement the
applications; the designer simply inferred or instantiated a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 6. FLEX 10K & FLEX 10KA Performance
Application
Resources
Used
LEs EABs
16-bit loadable
16
counter
(1)
16-bit accumulator
(1)
16
16-to-1 multiplexer
(2)
10
256
8 RAM read
0
cycle speed
(3)
256
8 RAM write
0
cycle speed
(3)
Notes:
(1)
The speed grade of this application is limited because of clock high and low specifications.
(2)
This application uses combinatorial inputs and outputs.
(3)
This application uses registered inputs and outputs.
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
shows FLEX 10K performance for some common designs. All
-1 Speed
-2 Speed
Grade
Grade
0
204
166
0
204
166
0
4.2
5.8
1
172
145
1
106
89
testing prior to
Performance
-3 Speed
-4 Speed
Grade
Grade
125
125
6.0
108
68
Units
95
MHz
95
MHz
7.0
ns
84
MHz
63
MHz
5