IC FLEX 10K FPGA 30K 208-RQFP

EPF10K30RI208-4

Manufacturer Part NumberEPF10K30RI208-4
DescriptionIC FLEX 10K FPGA 30K 208-RQFP
ManufacturerAltera
SeriesFLEX-10K®
EPF10K30RI208-4 datasheet
 


Specifications of EPF10K30RI208-4

Number Of Logic Elements/cells1728Number Of Labs/clbs216
Total Ram Bits12288Number Of I /o147
Number Of Gates69000Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case208-RQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2233  
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Table 36. Interconnect Timing Microparameters
Symbol
t
Delay from dedicated input pin to IOE control input
DIN2IOE
t
Delay from dedicated clock pin to LE or EAB clock
DCLK2LE
t
Delay from dedicated input or clock to LE or EAB data
DIN2DATA
t
Delay from dedicated clock pin to IOE clock
DCLK2IOE
t
Delay from dedicated input pin to LE or EAB control input
DIN2LE
t
Routing delay for an LE driving another LE in the same LAB
SAMELAB
t
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
SAMEROW
same row
t
Routing delay for an LE driving an IOE in the same column
SAMECOLUMN
t
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
DIFFROW
row
t
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
TWOROWS
t
Routing delay for an LE driving a control signal of an IOE via the peripheral
LEPERIPH
control bus
t
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
LABCARRY
different LE in a different LAB
t
Routing delay for the cascade-out signal of an LE driving the cascade-in
LABCASC
signal of a different LE in a different LAB
Table 37. External Timing Parameters
Symbol
t
Register-to-register delay via four LEs, three row interconnects, and four local
DRR
interconnects
t
Setup time with global clock at IOE register
INSU
t
Hold time with global clock at IOE register
INH
t
Clock-to-output delay with global clock at IOE register
OUTCO
Table 38. External Bidirectional Timing Parameters
Symbol
t
Setup time for bidirectional pins with global clock at adjacent LE register
INSUBIDIR
t
Hold time for bidirectional pins with global clock at adjacent LE register
INHBIDIR
t
Clock-to-output delay for bidirectional pins with global clock at IOE register
OUTCOBIDIR
t
Synchronous IOE output buffer disable delay
XZBIDIR
t
Synchronous IOE output buffer enable delay, slow slew rate = off
ZXBIDIR
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Note (1)
Parameter
Notes
(8),
(10)
Parameter
Note (10)
Parameter
Conditions
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
Conditions
(9)
Condition
63