XC3S250E-4TQG144C Xilinx Inc, XC3S250E-4TQG144C Datasheet - Page 101

• Manufacturer Part Number: XC3S250E-4TQG144C
• Description: IC SPARTAN-3E FPGA 250K 144TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4TQG144C

• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Total Ram Bits: 221184
• Number Of I /o: 108
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: 813-1009 - MODULE USB-TO-FPGA TOOL W/MANUAL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1524

JTAG Mode
For additional information, refer to the “JTAG Configuration
Mode and Boundary-Scan” chapter in UG332.
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG mode
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the
JTAG port after a power-on event or when PROG_B is
asserted. Selecting the JTAG mode simply disables the
other configuration modes. No other pins are required as
part of the configuration interface.
Figure 65
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
DS312-2 (v3.8) August 26, 2009
Product Specification
•
•
•
•
Internal memory
Disk drive
Over network
Over RF link
Configuration
Memory
Source
Download Host
Intelligent
illustrates a JTAG-only configuration interface.
R
•
•
•
•
Microcontroller
Processor
Tester
Computer
SERIAL_OUT
Recommend
open-drain
PROG_B
driver
VCC
GND
PROG_B
V
CLOCK
INIT_B
TMS
TDO
TCK
DONE
TDI
+2.5V
JTAG
Figure 64: Daisy-Chaining using Slave Serial Mode
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Spartan-3E
VCCINT
FPGA
+1.2V
GND
VCCAUX
VCCO_0
VCCO_2
www.xilinx.com
INIT_B
DONE
DOUT
TDO
VCCO_0
+2.5V
V
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
Design Note
If using software versions prior to ISE 9.1.01i, avoid config-
uring the FPGA using JTAG if...
•
•
The FPGA bitstream may be corrupted and the DONE pin
may go High. The following Answer Record contains addi-
tional information.
http://www.xilinx.com/support/answers/22255.htm
V
the mode pins are set for a Master mode
the attached Master mode PROM contains a valid
FPGA configuration bitstream.
+2.5V
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Spartan-3E
VCCINT
+1.2V
FPGA
GND
VCCAUX
VCCO_0
VCCO_2
INIT_B
DOUT
DONE
Functional Description
TDO
VCCO_0
VCCO_2
+2.5V
DS312-2_55_082009
CCLK
DOUT
PROG_B
DONE
INIT_B
TMS
TCK
101