AT40K40-2DQC Atmel, AT40K40-2DQC Datasheet
AT40K40-2DQC
Specifications of AT40K40-2DQC
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AT40K40-2DQC Summary of contents
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... Easy Migration to Atmel Gate Arrays for High Volume Production • Supply Voltage 5V for AT40K, and 3.3V for AT40KLV ™ ® ® ™ , Mentor , OrCAD , Synario , Synopsys ® ® , Synplicity 5K - 50K Gates Coprocessor FPGA with FreeRAM AT40K05 AT40K05LV AT40K10 AT40K10LV AT40K20 ® , AT40K20LV AT40K40 AT40K40LV Rev. 0896C–FPGA–04/02 ™ 1 ...
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... Cells 256 (1) Registers 256 RAM Bits 2,048 I/O (Maximum) 128 1. Packages with FCK will have 8 less registers. AT40K10 AT40K20 AT40K40 AT40K10LV AT40K20LV AT40K40LV 10K - 20K 20K - 30K 40K - 50K 576 1,024 (1) (1) 576 1,024 4,608 8,192 192 256 0896C–FPGA–04/02 ...
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... AT40K/AT40KLV series designs. Multiple design entry methods are supported. The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell’ ...
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... The Symmetrical At the heart of the Atmel architecture is a symmetrical array of identical cells, see Figure 1. The array is continuous from one edge to the other, except for bus repeat- Array ers spaced every four cells, see Figure 2 on page 5. At the intersection of each repeater row and column there RAM block accessible by adjacent buses ...
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Figure 2. Floor Plan (Representative Portion) Note: 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA = Vertical Repeater RV = Horizontal Repeater RH = Core Cell RAM RAM ...
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The Busing Network Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. Bus resources are connected via repeaters. Each ...
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Figure 3. Busing Plane (One of Five) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA = AT40K/AT40KLV Core Cell = Local/Local or Express/Express Turn Point = Row Repeater = Column Repeater Express Express Bus Bus Local Bus 7 ...
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Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing ...
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Figure 5. The Cell "1" "1" N "1" 8X1 LUT 8X1 LUT OUT OUT "0" "1" CLOCK RESET/SET ...
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Figure 6. Some Single Cell Modes CARRY AT40K/AT40KLV Series FPGA 10 Synthesis Mode. This mode is ...
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RAM dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to ...
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... RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM clear byte during configuration clears the RAM (see the “ AT40K Configuration Series” application note at www.atmel.com). Figure 8. RAM Logic WEN Figure 9 on page 13 shows an example of a RAM macro constructed using the AT40K/AT40KLV’ ...
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WE 2-to-4 Decoder Write Address Din(0) Din(1) Din(2) Din(3) Din Dout Ain Aout WEN OEN Din(4) Din(5) Din(6) Din(7) Din Dout Ain Aout WEN OEN Din Dout Din Dout Aout Ain Ain Aout WEN WEN OEN OEN Din Dout Din ...
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Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Glo- bal Clock pins. Any clocks used in the design ...
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Figure 10. Clocking (for One Column of Cells) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Express Bus (Plane 4; Half Length at Edge) Repeater } FCK (2 per Edge Column of the Array) GCK1 - GCK8 Column Clock Mux “1” ...
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Set/Reset Scheme The AT40K/AT40KLV family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking ...
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Figure 11. Set/Reset (for One Column of Cells) (Plane 5; Half Length at Edge) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Repeater “1” “1” Express Bus “1” “1” Any User I/O can Drive Global Set/Reset Lone Each Cell has a Programmable Set or ...
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I/O Structure PAD The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os have pads: the ones without pads are called Unbonded I/Os. The number of unbonded I/Os varies with the ...
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Primary, Secondary and The AT40K/AT40KLV has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40K/AT40KLV has access to one Pri- Corner I/Os mary I/O and two Secondary I/Os. ...
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Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV AT40K/AT40KLV Series FPGA 20 “0” “1” “0” PULL-UP “1” PAD PULL-DOWN (a) Primary I/O “0” “1” “0” PULL-UP “1” PAD PULL-DOWN (b) Secondary I/O CELL CELL CELL CELL CELL 0896C–FPGA–04/02 ...
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Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLV 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA (a) Primary I/O (a) Secondary I/O 21 ...
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Figure 14. Northwest Corner (Similar for NE/SE/SW Corners) AT40K/AT40KLV PULL-DOWN AT40K/AT40KLV Series FPGA 22 PAD VCC TTL/CMOS DRIVE SCHMITT TRI-STATE DELAY “0” “1” “0” PULL-UP “1” PAD PAD GND VCC GND TTL/CMOS DRIVE SCHMITT TRI-STATE DELAY CELL CELL CELL 0896C–FPGA–04/02 ...
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Absolute Maximum Ratings – 5V Commercial/Industrial* AT40K Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground .................................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum ...
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DC Characteristics – 5V Operation Commercial/Industrial/Military AT40K Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level ...
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AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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... GSRN AT40K10 pad -> GSRN AT40K20 pad -> GSRN AT40K40 clock pad -> out AT40K05 clock pad -> out AT40K10 clock pad -> out AT40K20 clock pad -> out AT40K40 clock pad -> out AT40K05 clock pad -> out AT40K10 clock pad -> out AT40K20 clock pad -> out AT40K40 of 50 ...
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AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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FreeRAM Asynchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA WE t AWS 0 ADDR OXZ DS DATA WE t AWS 0 WR ADDR PREV. WR DATA RD ADDR = WR ...
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FreeRAM Synchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read AT40K/AT40KLV Series FPGA 30 CLK t WCS WE t ACS 0 ADDR OE t OXZ t DCS DATA CLK t WCS WE t ACS 0 WR ADDR t ...
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Absolute Maximum Ratings – 3.3V Commercial/Industrial* AT40KLV Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground .................................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum ...
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DC Characteristics – 3.3V Operation Commercial/Industrial AT40KLV Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level ...
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AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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... GSRN AT40K10LV pad -> GSRN AT40K20LV pad -> GSRN AT40K40LV clock pad -> out AT40K05LV clock pad -> out AT40K10LV clock pad -> out AT40K20LV clock pad -> out AT40K40LV clock pad -> out AT40K05LV clock pad -> out AT40K10LV clock pad -> out AT40K20LV clock pad -> out AT40K40LV of 50 ...
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... OXZ Notes: 1. CMOS buffer delays are measured from Buffer delay pad voltage of 1.5V with one output switching. 3. Parameter based on characterization and simulation; not tested in production. 4. Exact power calculation is available in Atmel FPGA Designer software. AT40K/AT40KLV Series FPGA 36 = 3.0V, temperature = 70° 3.6V, temperature = 0°C ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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... Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. AT40K/AT40KLV Series FPGA 38 AT40K40 84 100 100 384 I/O PLCC PQFP TQFP ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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... I/O87 I/O88 I/O89 I/O90 22 19 GND I/O91 I/O92 I/O93 I/O94 I/O95 (3) (OTS) I/O96 GCK2 GND AT40K40 84 100 100 384 I/O PLCC PQFP TQFP VCC I/O97 GCK3 I/O98 (HDC) I/O99 I/O100 I/O101 32 29 Left Side (Top to Bottom) 144 160 208 240 LQFP ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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... GND I/O105 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. AT40K/AT40KLV Series FPGA 42 AT40K40 84 100 100 384 I/O PLCC PQFP TQFP ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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... AT40K/AT40KLV Series FPGA 44 AT40K40 84 100 100 384 I/O PLCC PQFP TQFP GND I/O187 I/O188 I/O189 I/O190 I/O191 (D8) I/O192 GCK4 GND CON AT40K40 84 100 100 384 I/O PLCC PQFP TQFP VCC RESET I/O193 (D7) I/O194 GCK5 I/O195 I/O196 I/O197 I/O198 GND I/O199 I/O200 ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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... I/O129 I/O173 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. AT40K/AT40KLV Series FPGA 46 AT40K40 84 100 100 384 I/O PLCC PQFP TQFP ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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... This package has an inverted die. 3. Shared with TSTCLK. No Connect. AT40K/AT40KLV Series FPGA 48 AT40K40 84 100 100 384 I/O PLCC PQFP TQFP CCLK VCC TSTCLK AT40K40 84 100 100 384 I/O PLCC PQFP TQFP GND I/O289 (A0) I/O290, GCK7 (A1) I/O291 I/O292 ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. AT40K/AT40KLV Series FPGA 50 AT40K40 84 100 100 384 I/O PLCC PQFP ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC PQFP ...
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Power and Ground Pinouts for 352 SBGA A10 A17 G23 H4 U26 W23 AE25 AF10 A1 A2 A25 A26 H26 N1 AE1 AE26 AF19 AF22 Note SBGA packages, Power and Ground pins do not connect directly to die. ...
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... Enhanced, Low-profile Square Ball Grid Array Package (SBGA) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K10/AT40K10LV 114 114 128 130 128 161 – – – – – – Package Type AT40K20/AT40K20LV AT40K40/AT40K40LV 62 – 77 – 78 – 114 114 130 – 161 161 193 193 – 256 – 289 53 ...
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... AT40K05/AT40K05LV Ordering Information Usable Gates Operating Voltage 5,000 - 10,000 5.0V 5,000 - 10,000 5.0V 5,000 - 10,000 3.3V 5,000 - 10,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. AT40K/AT40KLV Series FPGA 54 Speed Grade (ns) Ordering Code 2 AT40K05-2AJC AT40K05-2AQC AT40K05-2RQC AT40K05-2BQC AT40K05-2CQC AT40K05-2DQC 2 AT40K05-2AJI AT40K05-2AQI ...
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... AT40K10/AT40K10LV Ordering Information Usable Gates Operating Voltage 10,000 - 20,000 5.0V 10,000 - 20,000 5.0V 10,000 - 20,000 3.3V 10,000 - 20,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Speed Grade (ns) Ordering Code 2 AT40K10-2AJC AT40K10-2AQC AT40K10-2RQC AT40K10-2BQC AT40K10-2CQC AT40K10-2DQC ...
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... AT40K20/AT40K20LV Ordering Information Usable Gates Operating Voltage 20,000 - 30,000 5.0V 20,000 - 30,000 5.0V 20,000 - 30,000 3.3V 20,000 - 30,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com AT40K/AT40KLV Series FPGA 56 Speed Grade (ns) Ordering Code 2 AT40K20-2AJC AT40K20-2AQC AT40K20-2RQC AT40K20-2BQC AT40K20-2CQC AT40K20-2DQC AT40K20-2EQC 2 AT40K20-2AJI ...
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... Note: 1. For military parts, contact Atmel at fpga@atmel.com. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Speed Grade (ns) Ordering Code 2 AT40K40-2BQC AT40K40-2DQC AT40K40-2EQC AT40K40-2FQC AT40K40-2BGC 2 AT40K40-2BQI AT40K40-2DQI AT40K40-2EQI AT40K40-2FQI AT40K40-2BGI 3 AT40K40LV-2BQC AT40K40LV-2DQC AT40K40LV-2EQC AT40K40LV-2FQC ...
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Packaging Information 84J – PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) ...
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TQFP Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body ...
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PQFP E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation GC-1, for additional information determined at seating plane. 3. Regardless of ...
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LQFP Top View Side View 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. Notes: 2. The top package body size may be smaller than ...
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PQFP D1 E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation DD-1, for additional information determined at seating plane. 3. Regardless ...
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TQFP e Top View Bottom View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than ...
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PQFP D1 E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-029, Variation GA, for additional information. 2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994. ...
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PQFP D1 E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-029, Variation JA, for additional information. 2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994. ...
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SBGA A1 BALL CORNER D A1 BALL I.D. E Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-192, Variation BAR-2, for additional information. 2. JEDEC variations ...
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